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Boolean algebra. Combinational and sequential circuits. Minimization. Number representations and computer arithmetic (fixed and floating point)

$$\small{\overset{{\large{\textbf{Mark Distribution in Previous GATE}}}}{\begin{array}{|c|c|c|c|c|c|c|c|}\hline
\\\hline\textbf{1 Mark Count}&4&2&3&2&3&3&2&2.8&4
\\\hline\textbf{2 Marks Count}&2&2&0&4&2&0&0&1.7&4
\\\hline\textbf{Total Marks}&8&6&3&10&7&3&\bf{3}&\bf{6.2}&\bf{10}\\\hline

Hot questions in Digital Logic

59 votes
3 answers
Minimum No of Gates NAND/NOR Ex-OR Ex-Nor Half Adder Half Subtractor Full Adder Full Subtractor NAND ? ? ? ? ? ? NOR ? ? ? ? ? ?
asked Dec 18, 2015 in Digital Logic bahirNaik 62.1k views
77 votes
14 answers
We want to design a synchronous counter that counts the sequence $0-1-0-2-0-3$ and then repeats. The minimum number of $\text{J-K}$ flip-flops required to implement this counter is _____________.
asked Feb 12, 2016 in Digital Logic Sandeep Singh 21.3k views
61 votes
8 answers
A half adder is implemented with XOR and AND gates. A full adder is implemented with two half adders and one OR gate. The propagation delay of an XOR gate is twice that of an AND/OR gate. The propagation delay of an AND/OR gate is 1.2 microseconds ... ripple-carry binary adder is implemented by using four full adders. The total propagation time of this 4-bit binary adder in microseconds is ______.
asked Feb 13, 2015 in Digital Logic jothee 17.8k views
54 votes
6 answers
Consider a carry look ahead adder for adding two n-bit integers, built using gates of fan-in at most two. The time to perform addition using this adder is $\Theta (1)$ $\Theta (\log(n))$ $\Theta (\sqrt{n})$ $\Theta (n)$)
asked Feb 12, 2016 in Digital Logic Sandeep Singh 12.9k views
56 votes
9 answers
The minimum number of JK flip-flops required to construct a synchronous counter with the count sequence (0, 0, 1, 1, 2, 2, 3, 3, 0, 0, ...) is _______.
asked Feb 12, 2015 in Digital Logic jothee 16.8k views
10 votes
11 answers
What is the minimum number of $2$-input NOR gates required to implement a $4$ -variable function expressed in sum-of-minterms form as $f=\Sigma(0,2,5,7, 8, 10, 13, 15)?$ Assume that all the inputs and their complements are available. Answer: _______
asked Feb 7, 2019 in Digital Logic Arjun 9.1k views
54 votes
15 answers
A 4-bit carry look ahead adder, which adds two 4-bit numbers, is designed using AND, OR, NOT, NAND, NOR gates only. Assuming that all the inputs are available in both complemented and uncomplemented forms and the delay of each gate is one time unit, what is the ... Assume that the carry network has been implemented using two-level AND-OR logic. 4 time units 6 time units 10 time units 12 time units
asked Sep 19, 2014 in Digital Logic Kathleen 11.8k views
48 votes
9 answers
The n-bit fixed-point representation of an unsigned real number $X$ uses $f$ bits for the fraction part. Let $i = n-f$. The range of decimal values for $X$ in this representation is $2^{-f}$ to $2^{i}$ $2^{-f}$ to $\left ( 2^{i} - 2^{-f} \right )$ 0 to $2^{i}$ 0 to $\left ( 2^{i} - 2^{-f} \right )$
asked Feb 14, 2017 in Digital Logic Arjun 7k views
10 votes
5 answers
17 votes
7 answers
Two numbers are chosen independently and uniformly at random from the set $\{1,2,\ldots,13\}.$ The probability (rounded off to 3 decimal places) that their $4-bit$ (unsigned) binary representations have the same most significant bit is _______________.
asked Feb 7, 2019 in Digital Logic Arjun 7.2k views
28 votes
4 answers
Given the following binary number in $32$-bit (single precision) $IEEE-754$ format : $\large 00111110011011010000000000000000$ The decimal value closest to this floating-point number is : $1.45*10^1$ $1.45*10^{-1}$ $2.27*10^{-1}$ $2.27*10^1$
asked Feb 14, 2017 in Digital Logic khushtak 8.6k views
62 votes
5 answers
Consider numbers represented in 4-bit Gray code. Let $ h_{3}h_{2}h_{1}h_{0}$ be the Gray code representation of a number $n$ and let $ g_{3}g_{2}g_{1}g_{0}$ be the Gray code of $ (n+1)(modulo 16)$ ... $ g_{3}(h_{3}h_{2}h_{1}h_{0})=\sum (0,1,6,7,10,11,12,13) $
asked Sep 26, 2014 in Digital Logic Rucha Shelke 7.9k views
36 votes
6 answers
We consider the addition of two $2's$ complement numbers $ b_{n-1}b_{n-2}\dots b_{0}$ and $a_{n-1}a_{n-2}\dots a_{0}$. A binary adder for adding unsigned binary numbers is used to add the two numbers. The sum is denoted by $ c_{n-1}c_{n-2}\dots c_{0}$ and the carry-out by $ c_{out}$ ... $ c_{out}\oplus c_{n-1}$ $ a_{n-1}\oplus b_{n-1}\oplus c_{n-1}$
asked Sep 26, 2014 in Digital Logic Rucha Shelke 8.3k views
39 votes
9 answers
In the sequential circuit shown below, if the initial value of the output $Q_1Q_0$ is $00$. What are the next four values of $Q_1Q_0$? $11$, $10$, $01$, $00$ $10$, $11$, $01$, $00$ $10$, $00$, $01$, $11$ $11$, $10$, $00$, $01$
asked Sep 29, 2014 in Digital Logic jothee 9.4k views
11 votes
2 answers
What are the prime implicants and essential prime implicants for the below questions ? F(w, x, y, z) = ∑(1,2,5,7,12) + d(0,9,13) Explain by drawing K-map. Also explain the prime implicants and essential prime implicants with don't care condition .
asked Jul 19, 2017 in Digital Logic Kuldeep Pal 14.8k views
28 votes
6 answers
Consider the sequential circuit shown in the figure, where both flip-flops used are positive edge-triggered D flip-flops. The number of states in the state transition diagram of this circuit that have a transition back to the same state on some value of "in" is ____
asked Feb 14, 2018 in Digital Logic gatecse 7.2k views
47 votes
5 answers
You are given a free running clock with a duty cycle of $50\%$ and a digital waveform $f$ which changes only at the negative edge of the clock. Which one of the following circuits (using clocked D flip-flops) will delay the phase of $f$ by $180°$?
asked Sep 16, 2014 in Digital Logic Rucha Shelke 8.1k views
44 votes
6 answers
Suppose only one multiplexer and one inverter are allowed to be used to implement any Boolean function of $n$ variables. What is the minimum size of the multiplexer needed? $2^n$ line to $1$ line $2^{n+1}$ line to $1$line $2^{n-1}$ line to $1$line $2^{n-2}$ line to $1$line
asked Sep 22, 2014 in Digital Logic Kathleen 9.6k views
23 votes
7 answers
Consider a combination of T and D flip-flops connected as shown below. The output of the D flip-flop is connected to the input of the T flip-flop and the output of the T flip-flop is connected to the input of the D flip-flop. Initially, both $Q_{0}$ and $Q_{1}$ ... 00 and after the 4th cycle are 11 respectively. $Q_{1}Q_{0}$ after the 3rd cycle are 01 and after the 4th cycle are 01 respectively.
asked Feb 14, 2017 in Digital Logic Arjun 5k views
42 votes
8 answers
The following is a scheme for floating point number representation using 16 bits. Bit Position 15 14 .... 9 8 ...... 0 s e m Sign Exponent Mantissa Let s, e, and m be the numbers represented in binary in the sign, exponent, and mantissa fields respectively. Then the ... maximum difference between two successive real numbers representable in this system? $2^{-40}$ $2^{-9}$ $2^{22}$ $2^{31}$
asked Sep 17, 2014 in Digital Logic Kathleen 8.5k views