Boolean algebra. Combinational and sequential circuits. Minimization. Number representations and computer arithmetic (fixed and floating point)

$$\scriptsize{\overset{{\large{\textbf{Mark Distribution in Previous GATE}}}}{\begin{array}{|c|c|c|c|c|c|c|c|}\hline
\textbf{Year}& \textbf{2022} & \textbf{2021-1}&\textbf{2021-2}&\textbf{2020}&\textbf{2019}&\textbf{2018}&\textbf{2017-1}&\textbf{2017-2}&\textbf{2016-1}&\textbf{2016-2}&\textbf{Minimum}&\textbf{Average}&\textbf{Maximum}
\\\hline\textbf{1 Mark Count} & 1&2&3&2&4&2&3&2&3&3&1&2.5&4
\\\hline\textbf{2 Marks Count} & 2&2&2&1&2&2&0&4&2&0&0&1.7&4
\\\hline\textbf{Total Marks} & 5&6&7&4&8&6&3&10&7&3&\bf{3}&\bf{5.9}&\bf{10}\\\hline
\end{array}}}$$

Hot questions in Digital Logic

13 votes

2 answers

81

GATE CSE 2022 | Question: 30
Consider a digital display system $\text{(DDS)}$ shown in the figure that displays the contents of register $\text{X}.$ A $16 - \text{bit}$ code word is used to load a word in $\text{X},$ either from $\text{S}$ or from $\text{R}.$ $\text{S}$ is a $1024-$ ... $1:10$ de-multiplexer$; \quad \; \;\text{Q}$ is $1:5$ de-multiplexer$; \quad \text{T}$ is $2:1$ multiplexer

Consider a digital display system $\text{(DDS)}$ shown in the figure that displays the contents of register $\text{X}.$ A $16 – \text{bit}$ code word is used to load a...

4.9k views

Arjun asked Feb 15, 2022

8 votes

1 answer

82

GO Classes Test Series 2024 | Mock GATE | Test 11 | Question: 41
A self-dual logic function is a function that is identical to its dual. An anti-self-dual logic function is a function whose dual is the same as the complement of the function. A boolean function $f$ on $n$ variables is called neutral if $f$ has ... on $\mathrm{n}$ variables is $\mathrm{C}\left(2^{n-1}\right., \left.2^ {n-2}\right)$.

A self-dual logic function is a function that is identical to its dual. An anti-self-dual logic function is a function whose dual is the same as the complement of the fun...

752 views

GO Classes asked Jan 13

5 votes

2 answers

83

GO Classes Test Series 2024 | Mock GATE | Test 12 | Question: 53
Consider the following $4$-bit adder circuit. Note, $\text{C}_0$ is carry in and $\text{C}_4$ is carry out for the $4$-bit adder. The given circuit operates on $\text{2's}$ ... $\text{S}=1$

Consider the following $4$-bit adder circuit.Note, $\text{C}_0$ is carry in and $\text{C}_4$ is carry out for the $4$-bit adder. The given circuit operates on $\text{2's}...

679 views

GO Classes asked Jan 21

2 votes

2 answers

84

GO Classes Test Series 2024 | Mock GATE | Test 11 | Question: 39
The circuit shown below is designed using two multiplexers. This circuit is equivalent to: a positive edge triggered $\mathrm{T}$ flip flop a negative edge triggered $\mathrm{T}$ flip flop a negative edge triggered $\text{D}$ flip flop a positive edge triggered $\mathrm{D}$ flip flop

The circuit shown below is designed using two multiplexers.This circuit is equivalent to:a positive edge triggered $\mathrm{T}$ flip flopa negative edge triggered $\mathr...

819 views

GO Classes asked Jan 13

4 votes

1 answer

85

GO Classes Test Series 2024 | Mock GATE | Test 12 | Question: 21
How many $\text{4-to-1}$ multiplexers are needed to implement a $\text{64-to-1}$ multiplexer?

How many $\text{4-to-1}$ multiplexers are needed to implement a $\text{64-to-1}$ multiplexer?

407 views

GO Classes asked Jan 21

2 votes

1 answer

86

GO Classes Test Series 2024 | Mock GATE | Test 14 | Question: 59
Consider the shift register circuit shown in below figure. Assume that $\mathbf{I}_3 \mathbf{I}_2 \mathbf{I}_1 \mathbf{I}_0=0101$ has been loaded in the 4-bit register using the parallel load mechanism (i.e., shift=0 ... consecutive positive edges of the clock signal we need to keep shift=1 such that zero detect is activated to a 1?

Consider the shift register circuit shown in below figure. Assume that $\mathbf{I}_3 \mathbf{I}_2 \mathbf{I}_1 \mathbf{I}_0=0101$ has been loaded in the 4-bit register us...

520 views

GO Classes asked Feb 5

4 votes

2 answers

87

GO Classes Test Series 2024 | Mock GATE | Test 13 | Question: 60
You are asked to implement the following four functions with half-adders: ... of half-adders required to implement all four functions simultaneously? (You are not allowed to use any other logic element but half-adder)

You are asked to implement the following four functions with half-adders:$$\begin{aligned}& \mathrm{f}_1=A \oplus B \oplus C \\& \mathrm{f}_2=A^{\prime} B C+A B^{\prime} ...

487 views

GO Classes asked Jan 28

2 votes

1 answer

88

GO Classes Test Series 2024 | Mock GATE | Test 14 | Question: 28
Consider function $\mathbf{G}(\mathbf{A}, \mathbf{B}, \mathbf{C})=\mathbf{A B}+\mathbf{B C}$. Let $\mathbf{F}(\mathbf{A}, \mathbf{B}, \mathbf{C})$ ... input to a 2-to-1 multiplexer. The correct implementation of $\mathbf{F}(\mathbf{A}, \mathbf{B}, \mathbf{C})$ is shown in:

Consider function $\mathbf{G}(\mathbf{A}, \mathbf{B}, \mathbf{C})=\mathbf{A B}+\mathbf{B C}$. Let $\mathbf{F}(\mathbf{A}, \mathbf{B}, \mathbf{C})$ be the dual of $\mathbf...

509 views

GO Classes asked Feb 5

2 votes

3 answers

89

GO Classes Test Series 2024 | Mock GATE | Test 13 | Question: 59
For the circuit in the figure below, if the current state $\text{Q}_3\text{Q}_2\text{Q}_1\text{Q}_0$ is $6$ (in decimal) i.e. $\text{Q}_3\text{Q}_2\text{Q}_1\text{Q}_0=0110,$ then after the next positive edge of the clock signal the new state will be (in decimal)? (the flip-flops are positive edge triggered)

For the circuit in the figure below, if the current state $\text{Q}_3\text{Q}_2\text{Q}_1\text{Q}_0$ is $6$ (in decimal) i.e. $\text{Q}_3\text{Q}_2\text{Q}_1\text{Q}_0=01...

534 views

GO Classes asked Jan 28

1 votes

1 answer

90

GATE CSE 2024 | Set 2 | Question: 39
Which of the following is/are EQUAL to $224$ in radix - $5$ (i.e., base - $5$) notation? $64$ in radix -10 $100$ in radix -8 $50$ in radix -16 $121$ in radix -7

Which of the following is/are EQUAL to $224$ in radix - $5$ (i.e., base - $5$) notation?$64$ in radix -10$100$ in radix -8$50$ in radix -16$121$ in radix -7

1.7k views

Arjun asked Feb 16

3 votes

1 answer

91

GO Classes Test Series 2024 | Mock GATE | Test 12 | Question: 52
Consider the sequential circuit shown below. Consider the following state assignment: $\text{A}$ stands for $\text{Q = 0, B}$ stands for $\text{Q = 1}.$ The state transition diagram for the circuit above is shown in: a b c d

Consider the sequential circuit shown below.Consider the following state assignment: $\text{A}$ stands for $\text{Q = 0, B}$ stands for $\text{Q = 1}.$ The state transiti...

641 views

GO Classes asked Jan 21

4 votes

1 answer

92

GO Classes Test Series 2024 | Mock GATE | Test 11 | Question: 17
Consider the bit pattern $10110110.$ Interpret this bit pattern as a $8$-bit $2$'s complement number. What is the largest magnitude negative number that can be added to this value without causing $8$-bit $2$'s complement overflow? (Write your answer in decimal, only the magnitude, not the sign)

Consider the bit pattern $10110110.$ Interpret this bit pattern as a $8$-bit $2$'s complement number. What is the largest magnitude negative number that can be added to t...

584 views

GO Classes asked Jan 13

4 votes

1 answer

93

GO Classes Test Series 2024 | Mock GATE | Test 13 | Question: 26
The figure below represents the Karnaugh map for a function $\text{F(A,B,C,D).}$ Note, $\text{ X'}$ stands for don't care. The simplified logical expression in the sum-of-products (SOP) form (i.e., the minimum number of ... can be converted into a circuit implementation using only NAND gates, which is shown in: a b c d

The figure below represents the Karnaugh map for a function $\text{F(A,B,C,D).}$ Note, $\text{‘X’}$ stands for don’t care.The simplified logical expression in the s...

347 views

GO Classes asked Jan 28

4 votes

1 answer

94

GO Classes Test Series 2024 | Mock GATE | Test 11 | Question: 40
What is the output, $f(a,b,c,d),$ for the following circuit? $\Sigma(1,3,6,13,14,15)$ $\Sigma(1,3,6,9,10,14)$ $\Sigma(1,3,5,6,9,10,14)$ $\Sigma(1,3,5,6,9,10,12)$

What is the output, $f(a,b,c,d),$ for the following circuit?$\Sigma(1,3,6,13,14,15)$$\Sigma(1,3,6,9,10,14)$$\Sigma(1,3,5,6,9,10,14)$$\Sigma(1,3,5,6,9,10,12)$

544 views

GO Classes asked Jan 13

3 votes

0 answers

95

GO Classes Test Series 2024 | Mock GATE | Test 14 | Question: 60
The logic circuit above is used to compare two unsigned 2-bit numbers, $X_1 X_0=X$ and $Y_1 Y_0=Y$, where $X_0$ and $Y_0$ are the least significant bits. (A small circle on any line in a logic diagram indicates logical NOT.) Which of the following always makes the output $Z$ have the value 1? $X\gt Y$ $X\lt Y$ $X=Y$ $X \neq Y$

The logic circuit above is used to compare two unsigned 2-bit numbers, $X_1 X_0=X$ and $Y_1 Y_0=Y$, where $X_0$ and $Y_0$ are the least significant bits. (A small circle ...

338 views

GO Classes asked Feb 5

34 votes

5 answers

96

GATE IT 2005 | Question: 48
The circuit shown below implements a $\text{2-input}$ NOR gate using two $2-4$ MUX (control signal $1$ selects the upper input). What are the values of signals $x, y$ and $z$? $1, 0, B$ $1, 0, A$ $0, 1, B$ $0, 1, A$

The circuit shown below implements a $\text{2-input}$ NOR gate using two $2-4$ MUX (control signal $1$ selects the upper input). What are the values of signals $x, y$ and...

7.7k views

Ishrat Jahan asked Nov 3, 2014

0 votes

2 answers

97

GATE CSE 2024 | Set 1 | Question: 37
Consider a Boolean expression given by $\text{F(X, Y, Z)}=\sum(3,5,6,7)$. Which of the following statements is/are CORRECT? $\text{F(X, Y, Z)}=\Pi(0,1,2,4)$ $\text{F(X, Y, Z)=X Y+Y Z+X Z}$ $\text{F(X, Y, Z)}$ is independent of input $\text{Y}$ $\text{F(X, Y, Z)}$ is independent of input $\text{X}$

Consider a Boolean expression given by $\text{F(X, Y, Z)}=\sum(3,5,6,7)$.Which of the following statements is/are CORRECT?$\text{F(X, Y, Z)}=\Pi(0,1,2,4)$ $\text{F(X, Y, ...

2.0k views

Arjun asked Feb 16

0 votes

1 answer

98

GATE CSE 2024 | Set 2 | Question: 4
The format of a single-precision floating-point number as per the $\text{IEEE 754}$ standard is: Sign Exponent Mantissa $(1 \mathrm{bit})$ $(8 \mathrm{bits})$ $(23 \mathrm{bits})$ Choose the largest floating- ... $0$ $11111111$ $11111111111111111111111$ Sign Exponent Mantissa $0$ $01111111$ $00000000000000000000000$

The format of a single-precision floating-point number as per the $\text{IEEE 754}$ standard is:Sign ExponentMantissa$(1 \mathrm{bit})$ $(8 \mathrm{bits})$ $(23 \ma...

2.5k views

Arjun asked Feb 16

3 votes

1 answer

99

GO Classes Test Series 2024 | Mock GATE | Test 11 | Question: 16
Which one of the following options is CORRECT for the given logic circuit? $P=1, Q=1 ; X=0$ $P=1, Q=0 ; X=1$ $P=0, Q=1 ; X=0$ $P=0, Q=0 ; X=1$

Which one of the following options is CORRECT for the given logic circuit?$P=1, Q=1 ; X=0$$P=1, Q=0 ; X=1$$P=0, Q=1 ; X=0$$P=0, Q=0 ; X=1$

389 views

GO Classes asked Jan 13

2 votes

1 answer

100

GO Classes Test Series 2024 | Mock GATE | Test 12 | Question: 51
We would like to use a $\text{T}$ flip-flop and design a circuit that works like a $\text{J-K}$ flip-flop. The simplified input to the $\text{T}$ flip-flop should be: $\mathrm{T}=\mathrm{J}=\mathrm{K}$ $\text{T}=\text{JQ}^{\prime}+\text{K}^{\prime} Q$ $\text{T}=\text{JQ}^{\prime}+K Q$ $\text{T}=\text{JQ}+\text{KQ}'$

We would like to use a $\text{T}$ flip-flop and design a circuit that works like a $\text{J-K}$ flip-flop. The simplified input to the $\text{T}$ flip-flop should be:$\ma...

476 views

GO Classes asked Jan 21

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