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Boolean algebra. Combinational and sequential circuits. Minimization. Number representations and computer arithmetic (fixed and floating point)

$$\scriptsize{\overset{{\large{\textbf{Mark Distribution in Previous GATE}}}}{\begin{array}{|c|c|c|c|c|c|c|c|}\hline
\textbf{Year}& \textbf{2022} & \textbf{2021-1}&\textbf{2021-2}&\textbf{2020}&\textbf{2019}&\textbf{2018}&\textbf{2017-1}&\textbf{2017-2}&\textbf{2016-1}&\textbf{2016-2}&\textbf{Minimum}&\textbf{Average}&\textbf{Maximum}
\\\hline\textbf{1 Mark Count} & 1&2&3&2&4&2&3&2&3&3&1&2.5&4
\\\hline\textbf{2 Marks Count} & 2&2&2&1&2&2&0&4&2&0&0&1.7&4
\\\hline\textbf{Total Marks} & 5&6&7&4&8&6&3&10&7&3&\bf{3}&\bf{5.9}&\bf{10}\\\hline
\end{array}}}$$

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Most viewed questions in Digital Logic

41 votes
6 answers
21
GATE CSE 1999 | Question: 2.16
The number of full and half-adders required to add $16$-bit numbers is $8$ half-adders, $8$ full-adders $1$ half-adder, $15$ full-adders $16$ half-adders, $0$ full-adders $4$ half-adders, $12$ full-adders
The number of full and half-adders required to add $16$-bit numbers is$8$ half-adders, $8$ full-adders$1$ half-adder, $15$ full-adders$16$ half-adders, $0$ full-adders$4$...
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47 votes
9 answers
22
GATE CSE 2004 | Question: 18, ISRO2007-31
In an $SR$ latch made by cross-coupling two NAND gates, if both $S$ and $R$ inputs are set to $0$, then it will result in $Q = 0, Q' = 1$ $Q = 1, Q' = 0$ $Q = 1, Q' = 1$ Indeterminate states
In an $SR$ latch made by cross-coupling two NAND gates, if both $S$ and $R$ inputs are set to $0$, then it will result in$Q = 0, Q' = 1$$Q = 1, Q' = 0$$Q = 1, Q' = 1$Inde...
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3 votes
1 answer
23
Gate2009
What is minimum no of 2 to 1 MUX required to generate 2 input AND gate and 2 input ExOR gate A) 1& 2 B)1&3 C)1&1 D)2&2
What is minimum no of 2 to 1 MUX required to generate 2 input AND gate and 2 input ExOR gate A) 1& 2B)1&3C)1&1D)2&2
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34 votes
5 answers
27
GATE CSE 2007 | Question: 8, ISRO2011-31
How many $3$-to-$8$ line decoders with an enable input are needed to construct a $6$-to-$64$ line decoder without using any other logic gates? $7$ $8$ $9$ $10$
How many $3$-to-$8$ line decoders with an enable input are needed to construct a $6$-to-$64$ line decoder without using any other logic gates?$7$$8$$9$$10$
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52 votes
7 answers
29
GATE CSE 2015 Set 1 | Question: 20
Consider a $4$-bit Johnson counter with an initial value of $0000.$ The counting sequence of this counter is $0, 1, 3, 7, 15, 14, 12, 8, 0$ $0, 1, 3, 5, 7, 9, 11, 13, 15, 0$ $0, 2, 4, 6, 8, 10, 12, 14, 0$ $0, 8, 12, 14, 15, 7, 3, 1, 0$
Consider a $4$-bit Johnson counter with an initial value of $0000.$ The counting sequence of this counter is $0, 1, 3, 7, 15, 14, 12, 8, 0$$0, 1, 3, 5, 7, 9, 11, 13, 15, ...
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43 votes
6 answers
33
GATE CSE 2009 | Question: 6
What is the minimum number of gates required to implement the Boolean function $\text{(AB+C)}$ if we have to use only $2\text{-input NOR}$ gates? $2$ $3$ $4$ $5$
What is the minimum number of gates required to implement the Boolean function $\text{(AB+C)}$ if we have to use only $2\text{-input NOR}$ gates?$2$$3$$4$$5$
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66 votes
6 answers
36
GATE CSE 2007 | Question: 36
The control signal functions of a $4$-$bit$ binary counter are given below (where $X$ ... through the following sequence: $0, 3, 4$ $0, 3, 4, 5$ $0, 1, 2, 3, 4$ $0, 1, 2, 3, 4, 5$
The control signal functions of a $4$-$bit$ binary counter are given below (where $X$ is “don’t care”):$$\small {\begin{array}{|c|c|c|c|l|}\hline\textbf{Clear}& ...
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44 votes
5 answers
38
GATE CSE 2004 | Question: 61
Consider the partial implementation of a $2-bit$ counter using $T$ flip-flops following the sequence $0-2-3-1-0,$ as shown below. To complete the circuit, the input $X$ should be $Q_2^c$ $Q_2 + Q_1$ $\left(Q_1 + Q_2\right)^c$ $Q_1 \oplus Q_2$
Consider the partial implementation of a $2-bit$ counter using $T$ flip-flops following the sequence $0-2-3-1-0,$ as shown below.To complete the circuit, the input $X$ sh...
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56 votes
12 answers
39
GATE CSE 2015 Set 2 | Question: 37
The number of min-terms after minimizing the following Boolean expression is _______. $[D'+AB'+A'C+AC'D+A'C'D]'$
The number of min-terms after minimizing the following Boolean expression is _______.$[D'+AB'+A'C+AC'D+A'C'D]'$
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27 votes
5 answers
40
GATE CSE 2004 | Question: 66
Let $A = 1111 1010$ and $B = 0000 1010$ be two $8-bit$ $2’s$ complement numbers. Their product in $2’s$ complement is $1100 0100$ $1001 1100$ $1010 0101$ $1101 0101$
Let $A = 1111 1010$ and $B = 0000 1010$ be two $8-bit$ $2’s$ complement numbers. Their product in $2’s$ complement is$1100 0100$$1001 1100$$1010 0101$$1101 0101$
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