Boolean algebra. Combinational and sequential circuits. Minimization. Number representations and computer arithmetic (fixed and floating point)

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\textbf{Year}&\textbf{2021-1}&\textbf{2021-2}&\textbf{2020}&\textbf{2019}&\textbf{2018}&\textbf{2017-1}&\textbf{2017-2}&\textbf{2016-1}&\textbf{2016-2}&\textbf{Minimum}&\textbf{Average}&\textbf{Maximum}
\\\hline\textbf{1 Mark Count}&2&3&2&4&2&3&2&3&3&2&2.6&4
\\\hline\textbf{2 Marks Count}&2&2&1&2&2&0&4&2&0&0&1.6&4
\\\hline\textbf{Total Marks}&6&7&4&8&6&3&10&7&3&\bf{3}&\bf{6}&\bf{10}\\\hline
\end{array}}}$$

Highest voted questions in Digital Logic

103 votes

19 answers

GATE CSE 2016 Set 1 | Question: 8
We want to design a synchronous counter that counts the sequence $0-1-0-2-0-3$ and then repeats. The minimum number of $\text{J-K}$ flip-flops required to implement this counter is _____________.

Sandeep Singh asked in Digital Logic Feb 12, 2016

by Sandeep Singh

43.4k views

88 votes

11 answers

GATE CSE 2015 Set 2 | Question: 48
A half adder is implemented with XOR and AND gates. A full adder is implemented with two half adders and one OR gate. The propagation delay of an XOR gate is twice that of an AND/OR gate. The propagation delay of an AND/OR gate is ... adder is implemented by using four full adders. The total propagation time of this $4$-bit binary adder in microseconds is ______.

go_editor asked in Digital Logic Feb 13, 2015

by go_editor

34.8k views

86 votes

7 answers

GATE CSE 2015 Set 1 | Question: 39
Consider the operations $\textit{f (X, Y, Z) = X'YZ + XY' + Y'Z'}$ and $\textit{g (X, Y, Z) = X'YZ + X'YZ' + XY}$ Which one of the following is correct? Both $\left\{\textit{f} \right\}$ ... $\left\{ \textit{f}\right\}$ nor $\left\{\textit{g}\right\}$ is functionally complete

makhdoom ghaya asked in Digital Logic Feb 13, 2015

by makhdoom ghaya

18.9k views

83 votes

6 answers

GATE CSE 2006 | Question: 40
Consider numbers represented in 4-bit Gray code. Let $ h_{3}h_{2}h_{1}h_{0}$ be the Gray code representation of a number $n$ and let $ g_{3}g_{2}g_{1}g_{0}$ be the Gray code of $ (n+1)(modulo 16)$ ... $ g_{3}(h_{3}h_{2}h_{1}h_{0})=\sum (0,1,6,7,10,11,12,13) $

Rucha Shelke asked in Digital Logic Sep 26, 2014

by Rucha Shelke

15.4k views

76 votes

18 answers

GATE CSE 2004 | Question: 62
A 4-bit carry look ahead adder, which adds two 4-bit numbers, is designed using AND, OR, NOT, NAND, NOR gates only. Assuming that all the inputs are available in both complemented and uncomplemented forms and the delay of each gate is one time ... the carry network has been implemented using two-level AND-OR logic. 4 time units 6 time units 10 time units 12 time units

Kathleen asked in Digital Logic Sep 19, 2014

by Kathleen

22.8k views

75 votes

8 answers

GATE CSE 2016 Set 1 | Question: 33
Consider a carry look ahead adder for adding two $n$-bit integers, built using gates of fan-in at most two. The time to perform addition using this adder is $\Theta (1)$ $\Theta (\log(n))$ $\Theta (\sqrt{n})$ $\Theta (n)$)

Sandeep Singh asked in Digital Logic Feb 12, 2016

by Sandeep Singh

24.3k views

73 votes

8 answers

GATE CSE 2015 Set 2 | Question: 7
The minimum number of $\text{JK}$ flip-flops required to construct a synchronous counter with the count sequence $(0, 0, 1, 1, 2, 2, 3, 3, 0, 0, \ldots)$ is _______.

go_editor asked in Digital Logic Feb 12, 2015

by go_editor

29.8k views

67 votes

4 answers

Minimum NAND/NOR Gates - Realization for ExOR,ExNor,Adder,Subtractor
Minimum No of Gates NAND/NOR Ex-OR Ex-Nor Half Adder Half Subtractor Full Adder Full Subtractor NAND ? ? ? ? ? ? NOR ? ? ? ? ? ?

bahirNaik asked in Digital Logic Dec 18, 2015

by bahirNaik

76.9k views

63 votes

6 answers

GATE CSE 2006 | Question: 36
Given two three bit numbers $a_{2}a_{1}a_{0}$ and $b_{2}b_{1}b_{0}$ and $c$ ...

Rucha Shelke asked in Digital Logic Sep 22, 2014

by Rucha Shelke

11.8k views

63 votes

5 answers

GATE CSE 2006 | Question: 8
You are given a free running clock with a duty cycle of $50\%$ and a digital waveform $f$ which changes only at the negative edge of the clock. Which one of the following circuits (using clocked D flip-flops) will delay the phase of $f$ by $180°$?

Rucha Shelke asked in Digital Logic Sep 16, 2014

by Rucha Shelke

14.3k views

62 votes

6 answers

GATE CSE 2007 | Question: 36
The control signal functions of a $4$-$bit$ binary counter are given below (where $X$ ... through the following sequence: $0, 3, 4$ $0, 3, 4, 5$ $0, 1, 2, 3, 4$ $0, 1, 2, 3, 4, 5$

Kathleen asked in Digital Logic Sep 22, 2014

by Kathleen

15.5k views

62 votes

8 answers

GATE CSE 2003 | Question: 43
The following is a scheme for floating point number representation using $16$ bits. Let $s, e,$ and $m$ ... between two successive real numbers representable in this system? $2^{-40}$ $2^{-9}$ $2^{22}$ $2^{31}$

Kathleen asked in Digital Logic Sep 17, 2014

by Kathleen

14.5k views

61 votes

9 answers

GATE CSE 2017 Set 1 | Question: 7
The n-bit fixed-point representation of an unsigned real number $X$ uses $f$ bits for the fraction part. Let $i = n-f$. The range of decimal values for $X$ in this representation is $2^{-f}$ to $2^{i}$ $2^{-f}$ to $\left ( 2^{i} - 2^{-f} \right )$ 0 to $2^{i}$ 0 to $\left ( 2^{i} - 2^{-f} \right )$

Arjun asked in Digital Logic Feb 14, 2017

by Arjun

12.4k views

60 votes

7 answers

GATE CSE 2016 Set 2 | Question: 07
Consider an eight-bit ripple-carry adder for computing the sum of $A$ and $B$, where $A$ and $B$ are integers represented in $2$'s complement form. If the decimal value of $A$ is one, the decimal value of $B$ that leads to the longest latency for the sum to stabilize is ___________

Akash Kanase asked in Digital Logic Feb 12, 2016

by Akash Kanase

14.5k views

57 votes

8 answers

GATE CSE 2007 | Question: 34
Suppose only one multiplexer and one inverter are allowed to be used to implement any Boolean function of $n$ variables. What is the minimum size of the multiplexer needed? $2^n$ line to $1$ line $2^{n+1}$ line to $1$line $2^{n-1}$ line to $1$line $2^{n-2}$ line to $1$line

Kathleen asked in Digital Logic Sep 22, 2014

by Kathleen

25.3k views

56 votes

3 answers

GATE CSE 2006 | Question: 38
Consider a Boolean function $ f(w,x,y,z)$. Suppose that exactly one of its inputs is allowed to change at a time. If the function happens to be true for two input vectors $ i_{1}=\left \langle w_{1}, x_{1}, y_{1},z_{1}\right \rangle $ ... $ wx\overline{y} \overline{z}, xz, w\overline{x}yz$ $ wx\overline{y}, wyz, wxz, \overline{w}xz, x\overline{y}z, xyz$

Rucha Shelke asked in Digital Logic Sep 26, 2014

by Rucha Shelke

16.8k views

55 votes

5 answers

GATE CSE 2001 | Question: 2.8
Consider the following circuit with initial state $Q_0 = Q_1 = 0$. The D Flip-flops are positive edged triggered and have set up times 20 nanosecond and hold times $0.$ Consider the following timing diagrams of X and C. The clock period of $C \geq 40$ nanosecond. Which one is the correct plot of Y?

Kathleen asked in Digital Logic Sep 14, 2014

by Kathleen

16.6k views

55 votes

3 answers

GATE CSE 2005 | Question: 62
Consider the following circuit involving a positive edge triggered D FF. Consider the following timing diagram. Let $A_{i}$ represents the logic level on the line a in the i-th clock period. Let $A'$ represent the compliment of $A$. The correct output sequence on $Y$ over the clock periods $1$ ... $A_{1} A_{2} A_{2}' A_{3} A_{4}$ $A_{1} A_{2}' A_{3} A_{4} A_{5}'$

Isha Karn asked in Digital Logic Sep 3, 2014

by Isha Karn

13.8k views

53 votes

4 answers

GATE CSE 1991 | Question: 5-c
Find the maximum clock frequency at which the counter in the figure below can be operated. Assume that the propagation delay through each flip flop and each AND gate is $10\;\text{ns}$. Also, assume that the setup time for the $JK$ inputs of the flip flops is negligible.

ibia asked in Digital Logic Nov 14, 2015

by ibia

18.0k views

52 votes

1 answer

GATE CSE 2010 | Question: 7
The main memory unit with a capacity of $4$ $\text{megabytes}$ is built using $1\text{M} \times \text{1-bit}$ DRAM chips. Each DRAM chip has $1\text{K}$ rows of cells with $1\text{K}$ cells in each row. The time taken for a single ... in the memory unit is $100$ nanoseconds $100\times 2^{10}$ nanoseconds $100\times 2^{20}$ nanoseconds $3200\times 2^{20}$ nanoseconds

go_editor asked in Digital Logic Sep 29, 2014

by go_editor

15.6k views

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