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Boolean algebra. Combinational and sequential circuits. Minimization. Number representations and computer arithmetic (fixed and floating point)

$$\small{\overset{{\large{\textbf{Mark Distribution in Previous GATE}}}}{\begin{array}{|c|c|c|c|c|c|c|c|}\hline
\\\hline\textbf{1 Mark Count}&4&2&3&2&3&3&2&2.8&4
\\\hline\textbf{2 Marks Count}&2&2&0&4&2&0&0&1.7&4
\\\hline\textbf{Total Marks}&8&6&3&10&7&3&\bf{3}&\bf{6.2}&\bf{10}\\\hline

Highest voted questions in Digital Logic

85 votes
17 answers
We want to design a synchronous counter that counts the sequence $0-1-0-2-0-3$ and then repeats. The minimum number of $\text{J-K}$ flip-flops required to implement this counter is _____________.
asked Feb 12, 2016 in Digital Logic Sandeep Singh 27.7k views
72 votes
11 answers
A half adder is implemented with XOR and AND gates. A full adder is implemented with two half adders and one OR gate. The propagation delay of an XOR gate is twice that of an AND/OR gate. The propagation delay of an AND/OR gate is 1.2 microseconds ... ripple-carry binary adder is implemented by using four full adders. The total propagation time of this 4-bit binary adder in microseconds is ______.
asked Feb 13, 2015 in Digital Logic jothee 22.8k views
69 votes
6 answers
Consider numbers represented in 4-bit Gray code. Let $ h_{3}h_{2}h_{1}h_{0}$ be the Gray code representation of a number $n$ and let $ g_{3}g_{2}g_{1}g_{0}$ be the Gray code of $ (n+1)(modulo 16)$ ... $ g_{3}(h_{3}h_{2}h_{1}h_{0})=\sum (0,1,6,7,10,11,12,13) $
asked Sep 26, 2014 in Digital Logic Rucha Shelke 10.3k views
63 votes
3 answers
Minimum No of Gates NAND/NOR Ex-OR Ex-Nor Half Adder Half Subtractor Full Adder Full Subtractor NAND ? ? ? ? ? ? NOR ? ? ? ? ? ?
asked Dec 18, 2015 in Digital Logic bahirNaik 66.2k views
62 votes
8 answers
The minimum number of JK flip-flops required to construct a synchronous counter with the count sequence (0, 0, 1, 1, 2, 2, 3, 3, 0, 0, ...) is _______.
asked Feb 12, 2015 in Digital Logic jothee 21.9k views
61 votes
7 answers
Consider a carry look ahead adder for adding two n-bit integers, built using gates of fan-in at most two. The time to perform addition using this adder is $\Theta (1)$ $\Theta (\log(n))$ $\Theta (\sqrt{n})$ $\Theta (n)$)
asked Feb 12, 2016 in Digital Logic Sandeep Singh 16.2k views
60 votes
16 answers
A 4-bit carry look ahead adder, which adds two 4-bit numbers, is designed using AND, OR, NOT, NAND, NOR gates only. Assuming that all the inputs are available in both complemented and uncomplemented forms and the delay of each gate is one time unit, what is the ... Assume that the carry network has been implemented using two-level AND-OR logic. 4 time units 6 time units 10 time units 12 time units
asked Sep 19, 2014 in Digital Logic Kathleen 15.4k views
55 votes
6 answers
Given two three bit numbers $a_{2}a_{1}a_{0}$ and $b_{2}b_{1}b_{0}$ and $c$ ...
asked Sep 22, 2014 in Digital Logic Rucha Shelke 8.2k views
55 votes
6 answers
The control signal functions of a $4$-$bit$ binary counter are given below (where $X$ ... $0, 3, 4$ $0, 3, 4, 5$ $0, 1, 2, 3, 4$ $0, 1, 2, 3, 4, 5$
asked Sep 22, 2014 in Digital Logic Kathleen 11.6k views
54 votes
5 answers
You are given a free running clock with a duty cycle of $50\%$ and a digital waveform $f$ which changes only at the negative edge of the clock. Which one of the following circuits (using clocked D flip-flops) will delay the phase of $f$ by $180°$?
asked Sep 16, 2014 in Digital Logic Rucha Shelke 10.3k views
51 votes
9 answers
The n-bit fixed-point representation of an unsigned real number $X$ uses $f$ bits for the fraction part. Let $i = n-f$. The range of decimal values for $X$ in this representation is $2^{-f}$ to $2^{i}$ $2^{-f}$ to $\left ( 2^{i} - 2^{-f} \right )$ 0 to $2^{i}$ 0 to $\left ( 2^{i} - 2^{-f} \right )$
asked Feb 14, 2017 in Digital Logic Arjun 8.7k views
51 votes
6 answers
Consider an eight-bit ripple-carry adder for computing the sum of $A$ and $B$, where $A$ and $B$ are integers represented in $2$'s complement form. If the decimal value of $A$ is one, the decimal value of $B$ that leads to the longest latency for the sum to stabilize is ___________
asked Feb 12, 2016 in Digital Logic Akash Kanase 10.3k views
49 votes
4 answers
Find the maximum clock frequency at which the counter in the figure below can be operated. Assume that the propagation delay through each flip flop and each AND gate is $10$ $\text{ns}$. Also assume that the setup time for the $JK$ inputs of the flip flops is negligible.
asked Nov 14, 2015 in Digital Logic ibia 9.5k views
49 votes
8 answers
The following is a scheme for floating point number representation using 16 bits. Bit Position 15 14 .... 9 8 ...... 0 s e m Sign Exponent Mantissa Let s, e, and m be the numbers represented in binary in the sign, exponent, and mantissa fields respectively. Then the ... maximum difference between two successive real numbers representable in this system? $2^{-40}$ $2^{-9}$ $2^{22}$ $2^{31}$
asked Sep 17, 2014 in Digital Logic Kathleen 10.5k views
48 votes
7 answers
Suppose only one multiplexer and one inverter are allowed to be used to implement any Boolean function of $n$ variables. What is the minimum size of the multiplexer needed? $2^n$ line to $1$ line $2^{n+1}$ line to $1$line $2^{n-1}$ line to $1$line $2^{n-2}$ line to $1$line
asked Sep 22, 2014 in Digital Logic Kathleen 15k views
48 votes
5 answers
Consider the following circuit with initial state $Q_0 = Q_1 = 0$. The D Flip-flops are positive edged triggered and have set up times 20 nanosecond and hold times $0.$ Consider the following timing diagrams of X and C. The clock period of $C \geq 40$ nanosecond. Which one is the correct plot of Y?
asked Sep 14, 2014 in Digital Logic Kathleen 10.9k views
46 votes
3 answers
Consider a Boolean function $ f(w,x,y,z)$. Suppose that exactly one of its inputs is allowed to change at a time. If the function happens to be true for two input vectors $ i_{1}=\left \langle w_{1}, x_{1}, y_{1},z_{1}\right \rangle $ ... $ wx\overline{y} \overline{z}, xz, w\overline{x}yz$ $ wx\overline{y}, wyz, wxz, \overline{w}xz, x\overline{y}z, xyz$
asked Sep 26, 2014 in Digital Logic Rucha Shelke 11.7k views
46 votes
3 answers
In a look-ahead carry generator, the carry generate function $G_i$ and the carry propagate function $P_i$ for inputs $A_i$ and $B_i$ are given by: $P_i = A_i \oplus B_i \text{ and }G_i = A_iB_i$ The expressions for the sum bit $S_i$ and the carry bit $C_{i+1}$ of the look ahead carry ... 4-bit adder with $S_3, S_2, S_1, S_0$ and $C_4$ as its outputs are respectively: $6, 3$ $10, 4$ $6, 4$ $10, 5$
asked Sep 22, 2014 in Digital Logic Kathleen 6.2k views
46 votes
3 answers
Consider the following logic circuit whose inputs are functions $f_1, f_2, f_3$ and output is $f$ Given that $f_1(x,y,z) = \Sigma (0,1,3,5)$ $f_2(x,y,z) = \Sigma (6,7),$ and $f(x,y,z) = \Sigma (1,4,5).$ $f_3$ is $\Sigma (1,4,5)$ $\Sigma (6,7)$ $\Sigma (0,1,3,5)$ None of the above
asked Sep 16, 2014 in Digital Logic Kathleen 6.7k views
44 votes
3 answers
Consider the following circuit involving a positive edge triggered D FF. Consider the following timing diagram. Let $A_{i}$ represents the logic level on the line a in the i-th clock period. Let $A'$ represent the compliment of $A$. The correct output sequence on $Y$ over the clock periods $1$ through $5$ ... $A_{1} A_{2} A_{2}' A_{3} A_{4}$ $A_{1} A_{2}' A_{3} A_{4} A_{5}'$
asked Sep 3, 2014 in Digital Logic Isha Karn 9.6k views