Highest voted questions in Digital Logic

+74 votes

12 answers

1

GATE2016-1-8
We want to design a synchronous counter that counts the sequence $0-1-0-2-0-3$ and then repeats. The minimum number of $\text{J-K}$ flip-flops required to implement this counter is _____________.

asked Feb 12, 2016 in Digital Logic by Sandeep Singh Loyal (7.2k points) | 17.7k views

+56 votes

7 answers

2

GATE2015-2-48
A half adder is implemented with XOR and AND gates. A full adder is implemented with two half adders and one OR gate. The propagation delay of an XOR gate is twice that of an AND/OR gate. The propagation delay of an AND/OR gate is 1.2 ... -carry binary adder is implemented by using four full adders. The total propagation time of this 4-bit binary adder in microseconds is ______.

asked Feb 13, 2015 in Digital Logic by jothee Veteran (105k points) | 14.3k views

+55 votes

4 answers

3

GATE2006-40
Consider numbers represented in 4-bit Gray code. Let $ h_{3}h_{2}h_{1}h_{0}$ be the Gray code representation of a number $n$ and let $ g_{3}g_{2}g_{1}g_{0}$ be the Gray code of $ (n+1)(modulo 16)$ ... $ g_{3}(h_{3}h_{2}h_{1}h_{0})=\sum (0,1,6,7,10,11,12,13) $

asked Sep 26, 2014 in Digital Logic by Rucha Shelke Active (3.3k points) | 6.3k views

+53 votes

2 answers

4

Minimum NAND/NOR Gates - Realization for ExOR,ExNor,Adder,Subtractor
Minimum No of Gates NAND/NOR Ex-OR Ex-Nor Half Adder Half Subtractor Full Adder Full Subtractor NAND ? ? ? ? ? ? NOR ? ? ? ? ? ?

asked Dec 18, 2015 in Digital Logic by bahirNaik Active (3k points) | 59.6k views

+53 votes

9 answers

5

GATE2015-2-7
The minimum number of JK flip-flops required to construct a synchronous counter with the count sequence (0, 0, 1, 1, 2, 2, 3, 3, 0, 0, ...) is _______.

asked Feb 12, 2015 in Digital Logic by jothee Veteran (105k points) | 14k views

+49 votes

5 answers

6

GATE2016-1-33
Consider a carry look ahead adder for adding two n-bit integers, built using gates of fan-in at most two. The time to perform addition using this adder is $\Theta (1)$ $\Theta (\log(n))$ $\Theta (\sqrt{n})$ $\Theta (n)$)

asked Feb 12, 2016 in Digital Logic by Sandeep Singh Loyal (7.2k points) | 10.3k views

+49 votes

14 answers

7

GATE2004-62
A 4-bit carry look ahead adder, which adds two 4-bit numbers, is designed using AND, OR, NOT, NAND, NOR gates only. Assuming that all the inputs are available in both complemented and uncomplemented forms and the delay of each gate is one time unit, what ... that the carry network has been implemented using two-level AND-OR logic. 4 time units 6 time units 10 time units 12 time units

asked Sep 19, 2014 in Digital Logic by Kathleen Veteran (52.2k points) | 9.8k views

+47 votes

6 answers

8

GATE2007-36
The control signal functions of a $4$-$bit$ binary counter are given below (where $X$ ... cycles through the following sequence: $0, 3, 4$ $0, 3, 4, 5$ $0, 1, 2, 3, 4$ $0, 1, 2, 3, 4, 5$

asked Sep 22, 2014 in Digital Logic by Kathleen Veteran (52.2k points) | 7.3k views

+45 votes

5 answers

9

GATE2006-8
You are given a free running clock with a duty cycle of $50\%$ and a digital waveform $f$ which changes only at the negative edge of the clock. Which one of the following circuits (using clocked D flip-flops) will delay the phase of $f$ by $180°$?

asked Sep 16, 2014 in Digital Logic by Rucha Shelke Active (3.3k points) | 6.8k views

+44 votes

8 answers

10

GATE2017-1-7
The n-bit fixed-point representation of an unsigned real number $X$ uses $f$ bits for the fraction part. Let $i = n-f$. The range of decimal values for $X$ in this representation is $2^{-f}$ to $2^{i}$ $2^{-f}$ to $\left ( 2^{i} - 2^{-f} \right )$ 0 to $2^{i}$ 0 to $\left ( 2^{i} - 2^{-f} \right )$

asked Feb 14, 2017 in Digital Logic by Arjun Veteran (431k points) | 6k views

+42 votes

6 answers

11

GATE2006-36
Given two three bit numbers $a_{2}a_{1}a_{0}$ and $b_{2}b_{1}b_{0}$ and $c$ ...

asked Sep 22, 2014 in Digital Logic by Rucha Shelke Active (3.3k points) | 5.2k views

+40 votes

5 answers

12

GATE2016-2-07
Consider an eight-bit ripple-carry adder for computing the sum of $A$ and $B$, where $A$ and $B$ are integers represented in $2$'s complement form. If the decimal value of $A$ is one, the decimal value of $B$ that leads to the longest latency for the sum to stabilize is ___________

asked Feb 12, 2016 in Digital Logic by Akash Kanase Boss (41.9k points) | 6.7k views

+40 votes

2 answers

13

GATE2002-2-1
Consider the following logic circuit whose inputs are functions $f_1, f_2, f_3$ and output is $f$ Given that $f_1(x,y,z) = \Sigma (0,1,3,5)$ $f_2(x,y,z) = \Sigma (6,7),$ and $f(x,y,z) = \Sigma (1,4,5).$ $f_3$ is $\Sigma (1,4,5)$ $\Sigma (6,7)$ $\Sigma (0,1,3,5)$ None of the above

asked Sep 16, 2014 in Digital Logic by Kathleen Veteran (52.2k points) | 4.1k views

+40 votes

5 answers

14

GATE2001-2.8
Consider the following circuit with initial state $Q_0 = Q_1 = 0$. The D Flip-flops are positive edged triggered and have set up times 20 nanosecond and hold times $0.$ Consider the following timing diagrams of X and C. The clock period of $C \geq 40$ nanosecond. Which one is the correct plot of Y?

asked Sep 14, 2014 in Digital Logic by Kathleen Veteran (52.2k points) | 6.9k views

+39 votes

4 answers

15

GATE1991-5-c
Find the maximum clock frequency at which the counter in the figure below can be operated. Assume that the propagation delay through each flip flop and each AND gate is $10$ $\text{ns}$. Also assume that the setup time for the $JK$ inputs of the flip flops is negligible.

asked Nov 14, 2015 in Digital Logic by ibia Active (3.5k points) | 5.8k views

+39 votes

3 answers

16

GATE2007-35
In a look-ahead carry generator, the carry generate function $G_i$ and the carry propagate function $P_i$ for inputs $A_i$ and $B_i$ are given by: $P_i = A_i \oplus B_i \text{ and }G_i = A_iB_i$ The expressions for the sum bit $S_i$ and the carry bit $C_{i+1}$ of the look ... bit adder with $S_3, S_2, S_1, S_0$ and $C_4$ as its outputs are respectively: $6, 3$ $10, 4$ $6, 4$ $10, 5$

asked Sep 22, 2014 in Digital Logic by Kathleen Veteran (52.2k points) | 3.8k views

+39 votes

6 answers

17

GATE2007-34
Suppose only one multiplexer and one inverter are allowed to be used to implement any Boolean function of $n$ variables. What is the minimum size of the multiplexer needed? $2^n$ line to $1$ line $2^{n+1}$ line to $1$line $2^{n-1}$ line to $1$line $2^{n-2}$ line to $1$line

asked Sep 22, 2014 in Digital Logic by Kathleen Veteran (52.2k points) | 7.5k views

+38 votes

8 answers

18

GATE2003-43
The following is a scheme for floating point number representation using 16 bits. Bit Position 15 14 .... 9 8 ...... 0 s e m Sign Exponent Mantissa Let s, e, and m be the numbers represented in binary in the sign, exponent, and mantissa fields respectively. Then the ... difference between two successive real numbers representable in this system? $2^{-40}$ $2^{-9}$ $2^{22}$ $2^{31}$

asked Sep 17, 2014 in Digital Logic by Kathleen Veteran (52.2k points) | 6.7k views

+37 votes

4 answers

19

GATE2006-38
Consider a Boolean function $ f(w,x,y,z)$. Suppose that exactly one of its inputs is allowed to change at a time. If the function happens to be true for two input vectors $ i_{1}=\left \langle w_{1}, x_{1}, y_{1},z_{1}\right \rangle $ ... $ wx\overline{y} \overline{z}, xz, w\overline{x}yz$ $ wx\overline{y}, wyz, wxz, \overline{w}xz, x\overline{y}z, xyz$

asked Sep 26, 2014 in Digital Logic by Rucha Shelke Active (3.3k points) | 7.7k views

+35 votes

9 answers

20

GATE2010-32
In the sequential circuit shown below, if the initial value of the output $Q_1Q_0$ is $00$. What are the next four values of $Q_1Q_0$? $11$, $10$, $01$, $00$ $10$, $11$, $01$, $00$ $10$, $00$, $01$, $11$ $11$, $10$, $00$, $01$

asked Sep 29, 2014 in Digital Logic by jothee Veteran (105k points) | 7.1k views

+34 votes

4 answers

21

GATE2003-11
Consider an array multiplier for multiplying two $n$ bit numbers. If each gate in the circuit has a unit delay, the total delay of the multiplier is $\Theta(1)$ $\Theta(\log n)$ $\Theta(n)$ $\Theta(n^2)$

asked Sep 16, 2014 in Digital Logic by Kathleen Veteran (52.2k points) | 5k views

+33 votes

5 answers

22

GATE2015-1-20
Consider a 4-bit Johnson counter with an initial value of 0000. The counting sequence of this counter is 0, 1, 3, 7, 15, 14, 12, 8, 0 0, 1, 3, 5, 7, 9, 11, 13, 15, 0 0, 2, 4, 6, 8, 10, 12, 14, 0 0, 8, 12, 14, 15, 7, 3, 1, 0

asked Feb 13, 2015 in Digital Logic by makhdoom ghaya Boss (30.8k points) | 5.5k views

+33 votes

11 answers

23

GATE2004-18, ISRO2007-31
In an $SR$ latch made by cross-coupling two NAND gates, if both $S$ and $R$ inputs are set to $0$, then it will result in $Q = 0, Q' = 1$ $Q = 1, Q' = 0$ $Q = 1, Q' = 1$ Indeterminate states

asked Sep 19, 2014 in Digital Logic by Kathleen Veteran (52.2k points) | 6.7k views

+32 votes

6 answers

24

GATE2003-47
Consider the following circuit composed of XOR gates and non-inverting buffers. The non-inverting buffers have delays $\delta_1 = 2 ns$ and $\delta_2 = 4 ns$ as shown in the figure. Both XOR gates and all wires have zero delays. Assume that all gate inputs, outputs, and wires are stable ... change of logic levels) occur(s) at $B$ during the interval from $0$ to $10$ ns? $1$ $2$ $3$ $4$

asked Dec 2, 2015 in Digital Logic by shikharV Active (3.5k points) | 5.6k views

+32 votes

1 answer

25

GATE2010-7
The main memory unit with a capacity of $4$ $\text{megabytes}$ is built using $1M \times$ $\text{1-bit}$ DRAM chips. Each DRAM chip has 1K rows of cells with $1K$ cells in each row. The time taken for a single refresh operation is $100$ ... in the memory unit is $100$ nanoseconds $100\times 2^{10}$ nanoseconds $100\times 2^{20}$ nanoseconds $3200\times 2^{20}$ nanoseconds

asked Sep 29, 2014 in Digital Logic by jothee Veteran (105k points) | 7.3k views

+32 votes

5 answers

26

GATE2014-2-7
Let $k=2^n$. A circuit is built by giving the output of an $n$-bit binary counter as input to an $n\text{-to-}2^n$ bit decoder. This circuit is equivalent to a $k$-bit binary up counter. $k$-bit binary down counter. $k$--bit ring counter. $k$-bit Johnson counter.

asked Sep 28, 2014 in Digital Logic by jothee Veteran (105k points) | 6.1k views

+32 votes

5 answers

27

GATE2006-39
We consider the addition of two $2's$ complement numbers $ b_{n-1}b_{n-2}\dots b_{0}$ and $a_{n-1}a_{n-2}\dots a_{0}$. A binary adder for adding unsigned binary numbers is used to add the two numbers. The sum is denoted by $ c_{n-1}c_{n-2}\dots c_{0}$ ... $ c_{out}\oplus c_{n-1}$ $ a_{n-1}\oplus b_{n-1}\oplus c_{n-1}$

asked Sep 26, 2014 in Digital Logic by Rucha Shelke Active (3.3k points) | 6.9k views

+32 votes

3 answers

28

GATE2005-62
Consider the following circuit involving a positive edge triggered D FF. Consider the following timing diagram. Let $A_{i}$ represents the logic level on the line a in the i-th clock period. Let $A'$ represent the compliment of $A$. The correct output sequence on $Y$ over the clock periods $1$ through $5$ is: ... $A_{1} A_{2} A_{2}' A_{3} A_{4}$ $A_{1} A_{2}' A_{3} A_{4} A_{5}'$

asked Sep 3, 2014 in Digital Logic by Isha Karn (459 points) | 6.2k views

+31 votes

4 answers

29

GATE2007-48
Which of the following is TRUE about formulae in Conjunctive Normal Form? For any formula, there is a truth assignment for which at least half the clauses evaluate to true. For any formula, there is a truth assignment for which all the clauses evaluate to true. There is a formula such that for each truth assignment, at most one-fourth of the clauses evaluate to true. None of the above.

asked Sep 22, 2014 in Digital Logic by Kathleen Veteran (52.2k points) | 4.9k views

+31 votes

6 answers

30

GATE2003-45
The literal count of a Boolean expression is the sum of the number of times each literal appears in the expression. For example, the literal count of $\left(xy+xz'\right)$ is $4.$ What are the minimum possible literal counts of the product-of-sum and sum-of-product representations respectively of ... map? Here, $X$ denotes "don't care" $(11, 9)$ $(9, 13)$ $(9, 10)$ $(11,11)$

asked Sep 17, 2014 in Digital Logic by Kathleen Veteran (52.2k points) | 5k views

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