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Boolean algebra. Combinational and sequential circuits. Minimization. Number representations and computer arithmetic (fixed and floating point)

$$\scriptsize{\overset{{\large{\textbf{Mark Distribution in Previous GATE}}}}{\begin{array}{|c|c|c|c|c|c|c|c|}\hline
\textbf{Year}& \textbf{2022} & \textbf{2021-1}&\textbf{2021-2}&\textbf{2020}&\textbf{2019}&\textbf{2018}&\textbf{2017-1}&\textbf{2017-2}&\textbf{2016-1}&\textbf{2016-2}&\textbf{Minimum}&\textbf{Average}&\textbf{Maximum}
\\\hline\textbf{1 Mark Count} & 1&2&3&2&4&2&3&2&3&3&1&2.5&4
\\\hline\textbf{2 Marks Count} & 2&2&2&1&2&2&0&4&2&0&0&1.7&4
\\\hline\textbf{Total Marks} & 5&6&7&4&8&6&3&10&7&3&\bf{3}&\bf{5.9}&\bf{10}\\\hline
\end{array}}}$$

Highest voted questions in Digital Logic

52 votes
7 answers
33
48 votes
4 answers
35
Consider an array multiplier for multiplying two $n$ bit numbers. If each gate in the circuit has a unit delay, the total delay of the multiplier is$\Theta(1)$$\Theta(\lo...
47 votes
5 answers
36
Which of the following input sequences for a cross-coupled $R-S$ flip-flop realized with two $NAND$ gates may lead to an oscillation?$11, 00$$01, 10$$10, 01$$00, 11$
47 votes
9 answers
37
In an $SR$ latch made by cross-coupling two NAND gates, if both $S$ and $R$ inputs are set to $0$, then it will result in$Q = 0, Q' = 1$$Q = 1, Q' = 0$$Q = 1, Q' = 1$Inde...
47 votes
5 answers
38
Consider the circuit shown below. The output of a $2:1$ MUX is given by the function $(ac' + bc)$.Which of the following is true?$f=X_1'+X_2$$f=X_1'X_2+X_1X_2'$$f=X_1X_2+...
44 votes
7 answers
45
44 votes
5 answers
46
43 votes
6 answers
48
What is the minimum number of gates required to implement the Boolean function $\text{(AB+C)}$ if we have to use only $2\text{-input NOR}$ gates?$2$$3$$4$$5$
43 votes
6 answers
49
43 votes
3 answers
50
The amount of ROM needed to implement a $4\text{-bit}$ multiplier is$64$ bits$128$ bits$1$ Kbits$2$ Kbits