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Boolean algebra. Combinational and sequential circuits. Minimization. Number representations and computer arithmetic (fixed and floating point)

$$\small{\overset{{\large{\textbf{Mark Distribution in Previous GATE}}}}{\begin{array}{|c|c|c|c|c|c|c|c|}\hline
\textbf{Year}&\textbf{2019}&\textbf{2018}&\textbf{2017-1}&\textbf{2017-2}&\textbf{2016-1}&\textbf{2016-2}&\textbf{Minimum}&\textbf{Average}&\textbf{Maximum}
\\\hline\textbf{1 Mark Count}&4&2&3&2&3&3&2&2.8&4
\\\hline\textbf{2 Marks Count}&2&2&0&4&2&0&0&1.7&4
\\\hline\textbf{Total Marks}&8&6&3&10&7&3&\bf{3}&\bf{6.2}&\bf{10}\\\hline
\end{array}}}$$

Recent questions in Digital Logic

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1
Define a Boolean function $F(X_1, X_2, X_3, X_4, X_5, X_6)$ of six variables such that $\\ \begin{array}{llll} F & = & 1, & \text{when three or more input variables are at logic 1} \\ { } & = & 0, & \text{otherwise} \end{array} $ How many essential prime implicants does $F$ have? Justify they are essential.
asked Apr 8, 2019 in Digital Logic akash.dinkar12 159 views
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2
For the asynchronous sequential circuit shown in the figure: Derive the boolean functions for the outputs of two SR latches $Y _1 and Y _2$. Note that the S input of the second latch is $x _1’y _1’$. Derive the transition table and output map of the circuit.
asked Apr 7, 2019 in Digital Logic ajaysoni1924 304 views
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3
Convert the circuit of the figure to the asynchronous sequential circuit by removing the clock-pulse(CP) and changes the flip-flops to the SR latches. Derive the transition table and output map of the modified circuit.
asked Apr 7, 2019 in Digital Logic ajaysoni1924 101 views
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5
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6
Convert the flow table of the figure into a transition table by assigning the following binary values to the states: a = 00, b = 11, and c = 10. Assign values to the extra fourth state to avoid critical races. Assign output to the don’t care states to avoid momentary false output. Derive the logic diagram of the circuit.
asked Apr 7, 2019 in Digital Logic ajaysoni1924 162 views
1 vote
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7
An asynchronous sequential circuit has two internal states and one output. The excitation and output functions describing the circuit are as follows. $Y _1 = x _1x _2 + x _1y _2’ + x _2’y _1$ $Y _2 = x _2 + x _1y _1’y _2 + x _1’y _1$ $z = x _2 + y _1$ Draw the logic diagram of the circuit. Derive the transition table and the output map. Obtain a flow table for the circuit.
asked Apr 7, 2019 in Digital Logic ajaysoni1924 973 views
1 vote
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8
an asynchronous circuit is described by the following excitation and output functions: $Y = x _1x _2’ + (x _1 + x _2’)y$ $z = y$ Draw the logic diagram of the circuit. Derive the transition table and the output map. obtain a two-state flow table. Describe in the words the behavior of the circuit.
asked Apr 7, 2019 in Digital Logic ajaysoni1924 183 views
1 vote
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9
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10
Explain the difference between synchronous and asynchronous sequential circuits. Define fundamental mode operation. Explain the difference between stable and unstable states. what is the difference between an internal state or a total state?
asked Apr 7, 2019 in Digital Logic ajaysoni1924 42 views
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11
It is necessary to formulate the hamming code for four data bits $D _3, D _5, D _6 and D _7$ together with three parity bits $P _1, P _2 and P _3$ ... to include the double bit error detection in the code. Assume that error occurs in the bit $D _5 and P _2$. Show how the error is detected.
asked Apr 6, 2019 in Digital Logic ajaysoni1924 247 views
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12
How many parity check bits must be included with the data word to achieve single-bit error correction and double error correction when data words are as follows: 16 bits 32 bits 48 bits
asked Apr 6, 2019 in Digital Logic ajaysoni1924 1k views
1 vote
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13
A 12-bit hamming code word 8-bits of data and 4 parity bits are read from the memory. What was the original 8-bit data word that was written into the memory if the 12-bits word read out are as follows: 000011101010 101110000110 101111110100
asked Apr 6, 2019 in Digital Logic ajaysoni1924 328 views
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1 answer
14
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15
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16
An integrated circuit ram chip has a capacity of 1024 words of 8 bits each ($1K \times 8$) How many addresses and the data lines are there in the chips? How many chips are needed to construct a $16K \times 16$ ram? How many addresses and the data lines are there ... construct $16k \times 16$ memory from the $1 \times 8$ chips? What are the input to the decoder and where are its output connected?
asked Apr 6, 2019 in Digital Logic ajaysoni1924 95 views
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17
A computer uses RAM chips of $1024 \times 1$ capacity. how many chips are needed and how should there address line should be connected to provide a memory capacity of 1024 bytes. how many chips are needed to provide a memory capacity of 16K bytes? Explain in the words how chips are connected.
asked Apr 6, 2019 in Digital Logic ajaysoni1924 59 views
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18
How many $128 \times 8$ RAM chips are needed to provide a memory capacity of 2048 bytes? How many lines of the address must be used to access 2048 bytes? How many of these lines are connected to the address inputs of all the chips? How many lines must be decoded for the chip select inputs?Specify the size of the decoder?
asked Apr 6, 2019 in Digital Logic ajaysoni1924 245 views
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19
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20
The following memory units are specified by the number of words times the number of bits per word. How many address lines and Input output data lines are needed in each case given below? $2K \times 16$; $64K \times 8$; $16M \times 32$; $96K \times 12$;
asked Apr 6, 2019 in Digital Logic ajaysoni1924 80 views
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