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Boolean algebra. Combinational and sequential circuits. Minimization. Number representations and computer arithmetic (fixed and floating point)

$$\scriptsize{\overset{{\large{\textbf{Mark Distribution in Previous GATE}}}}{\begin{array}{|c|c|c|c|c|c|c|c|}\hline
\textbf{Year}& \textbf{2022} & \textbf{2021-1}&\textbf{2021-2}&\textbf{2020}&\textbf{2019}&\textbf{2018}&\textbf{2017-1}&\textbf{2017-2}&\textbf{2016-1}&\textbf{2016-2}&\textbf{Minimum}&\textbf{Average}&\textbf{Maximum}
\\\hline\textbf{1 Mark Count} & 1&2&3&2&4&2&3&2&3&3&1&2.5&4
\\\hline\textbf{2 Marks Count} & 2&2&2&1&2&2&0&4&2&0&0&1.7&4
\\\hline\textbf{Total Marks} & 5&6&7&4&8&6&3&10&7&3&\bf{3}&\bf{5.9}&\bf{10}\\\hline
\end{array}}}$$

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Recent questions in Digital Logic

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1862
UGC NET CSE | December 2009 | Part 2 | Question: 08
The highest noise margin is offered by $\text{BICMOS}$ $\text{TTL}$ $\text{ECL}$ $\text{CMOS}$
The highest noise margin is offered by$\text{BICMOS}$$\text{TTL}$$\text{ECL}$$\text{CMOS}$
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1 votes
1 answer
1863
UGC NET CSE | December 2009 | Part 2 | Question: 06
The simplified form of the Boolean expression (X + Y + XY) (X + Z) is (A) X + Y + ZX + Y (B) XY – YZ (C) X + YZ (D) XZ + Y
The simplified form of the Boolean expression (X + Y + XY) (X + Z) is(A) X + Y + ZX + Y(B) XY – YZ(C) X + YZ(D) XZ + Y
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1864
Made easy book
consider one sets of mod-14 digital-counter having input clock frequncy 19khz if another frequency as first is cascaded then final output clock frequency of composite counter will be
consider one sets of mod-14 digital-counter having input clock frequncy 19khz if another frequency as first is cascaded then final output clock frequency of composite cou...
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1866
flip flops
is there any way to find the number of flip flops usingclock period and proportional delay?
is there any way to find the number of flip flops usingclock period and proportional delay?
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1 answer
1868
number system
what is the probability of overflow occurring in addition of two 3-bit signed 2's complement number?
what is the probability of overflow occurring in addition of two 3-bit signed 2's complement number?
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2 answers
1869
when an inverter is placed in both inputs of SR flip flop
When an inverter is placed between both inputs of an SR flip-flop, the resulting flip-flop is [A]. JK flip-flop [B]. D flip-flop [C]. T flip-flop [D]. Master slave JK flip-flop ans given is B but how
When an inverter is placed between both inputs of an SR flip-flop, the resulting flip-flop is[A].JK flip-flop[B].D flip-flop [C].T flip-flop[D].Master slave JK flip-flopa...
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1 votes
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1874
Digital Systems - 2-bit Equality Detector to 4-bit Equality Detector
Modify the following 2-bit equality detector into a 4-bit equality detector:
Modify the following 2-bit equality detector into a 4-bit equality detector:
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1 votes
1 answer
1875
gate 2015 ECE
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4 votes
1 answer
1876
Boolean Algebra Properties
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3 votes
1 answer
1877
Boolean Algebra
Could someone solve this, i think i am making some mistake
Could someone solve this, i think i am making some mistake
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2 votes
1 answer
1879
Excess 3
In Excess 3 addition, the groups that have produced a carry we have to add 0011 to them and subtract 0011 from the groups which have not produced a carry during the addition. Can someone explain the logic of performing this step for me?
In Excess 3 addition, the groups that have produced a carry we have to add 0011 to them and subtract 0011 from the groups which have not produced a carry during the addit...
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1 votes
1 answer
1880
FLIP FLOP
Which of the following are true: 1. Race around condition occurs in a SR f/f When both the input S=R=1. 2. A transparent latch consist of a D F/F. 3. Edge triggered f/f removes the race condition. 4.Master slave configuration is used in f/f to store two bits of information.
Which of the following are true:1. Race around condition occurs in a SR f/f When both the input S=R=1.2. A transparent latch consist of a D F/F.3. Edge triggered f/f remo...
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