Boolean algebra. Combinational and sequential circuits. Minimization. Number representations and computer arithmetic (fixed and floating point)

$$\scriptsize{\overset{{\large{\textbf{Mark Distribution in Previous GATE}}}}{\begin{array}{|c|c|c|c|c|c|c|c|}\hline
\textbf{Year}& \textbf{2022} & \textbf{2021-1}&\textbf{2021-2}&\textbf{2020}&\textbf{2019}&\textbf{2018}&\textbf{2017-1}&\textbf{2017-2}&\textbf{2016-1}&\textbf{2016-2}&\textbf{Minimum}&\textbf{Average}&\textbf{Maximum}
\\\hline\textbf{1 Mark Count} & 1&2&3&2&4&2&3&2&3&3&1&2.5&4
\\\hline\textbf{2 Marks Count} & 2&2&2&1&2&2&0&4&2&0&0&1.7&4
\\\hline\textbf{Total Marks} & 5&6&7&4&8&6&3&10&7&3&\bf{3}&\bf{5.9}&\bf{10}\\\hline
\end{array}}}$$

Recent questions in Digital Logic

5 votes

2 answers

GO Classes Test Series 2024 | Mock GATE | Test 12 | Question: 53
Consider the following $4$-bit adder circuit. Note, $\text{C}_0$ is carry in and $\text{C}_4$ is carry out for the $4$-bit adder. The given circuit operates on $\text{2's}$ ... $\text{S}=1$

Consider the following $4$-bit adder circuit.Note, $\text{C}_0$ is carry in and $\text{C}_4$ is carry out for the $4$-bit adder. The given circuit operates on $\text{2's}...

GO Classes

690 views

GO Classes asked Jan 21

0 votes

0 answers

Byjus Mock Test
I am unable to understand the language of the question , can someone help me??

I am unable to understand the language of the question , can someone help me??

Dadu

149 views

Dadu asked Jan 15

3 votes

1 answer

GO Classes Test Series 2024 | Mock GATE | Test 11 | Question: 16
Which one of the following options is CORRECT for the given logic circuit? $P=1, Q=1 ; X=0$ $P=1, Q=0 ; X=1$ $P=0, Q=1 ; X=0$ $P=0, Q=0 ; X=1$

Which one of the following options is CORRECT for the given logic circuit?$P=1, Q=1 ; X=0$$P=1, Q=0 ; X=1$$P=0, Q=1 ; X=0$$P=0, Q=0 ; X=1$

GO Classes

394 views

GO Classes asked Jan 13

4 votes

1 answer

GO Classes Test Series 2024 | Mock GATE | Test 11 | Question: 17
Consider the bit pattern $10110110.$ Interpret this bit pattern as a $8$-bit $2$'s complement number. What is the largest magnitude negative number that can be added to this value without causing $8$-bit $2$'s complement overflow? (Write your answer in decimal, only the magnitude, not the sign)

Consider the bit pattern $10110110.$ Interpret this bit pattern as a $8$-bit $2$'s complement number. What is the largest magnitude negative number that can be added to t...

GO Classes

591 views

GO Classes asked Jan 13

2 votes

2 answers

GO Classes Test Series 2024 | Mock GATE | Test 11 | Question: 39
The circuit shown below is designed using two multiplexers. This circuit is equivalent to: a positive edge triggered $\mathrm{T}$ flip flop a negative edge triggered $\mathrm{T}$ flip flop a negative edge triggered $\text{D}$ flip flop a positive edge triggered $\mathrm{D}$ flip flop

The circuit shown below is designed using two multiplexers.This circuit is equivalent to:a positive edge triggered $\mathrm{T}$ flip flopa negative edge triggered $\mathr...

GO Classes

833 views

GO Classes asked Jan 13

4 votes

1 answer

GO Classes Test Series 2024 | Mock GATE | Test 11 | Question: 40
What is the output, $f(a,b,c,d),$ for the following circuit? $\Sigma(1,3,6,13,14,15)$ $\Sigma(1,3,6,9,10,14)$ $\Sigma(1,3,5,6,9,10,14)$ $\Sigma(1,3,5,6,9,10,12)$

What is the output, $f(a,b,c,d),$ for the following circuit?$\Sigma(1,3,6,13,14,15)$$\Sigma(1,3,6,9,10,14)$$\Sigma(1,3,5,6,9,10,14)$$\Sigma(1,3,5,6,9,10,12)$

GO Classes

546 views

GO Classes asked Jan 13

8 votes

1 answer

GO Classes Test Series 2024 | Mock GATE | Test 11 | Question: 41
A self-dual logic function is a function that is identical to its dual. An anti-self-dual logic function is a function whose dual is the same as the complement of the function. A boolean function $f$ on $n$ variables is called neutral if $f$ has ... on $\mathrm{n}$ variables is $\mathrm{C}\left(2^{n-1}\right., \left.2^ {n-2}\right)$.

A self-dual logic function is a function that is identical to its dual. An anti-self-dual logic function is a function whose dual is the same as the complement of the fun...

GO Classes

755 views

GO Classes asked Jan 13

0 votes

1 answer

GATE 2018 MOCK | GFG | Digital Logic
IEEE Standard 754 floating point is the most common representation today for real numbers on computers. The diagram below shows these parts are store--d in memory: The IEEE 754 standard includes special cases for numbers that are difficult to represent, ... $+/-$ Denormalized number (C) Code-3 represented $+/-$ Infinity (D) Code-4 represented number Zero

IEEE Standard 754 floating point is the most common representation today for real numbers on computers. The diagram below shows these parts are store d in memory:The IEEE...

rajveer43

153 views

rajveer43 asked Jan 12

0 votes

1 answer

GATE CS Mock 2018 | Question 60 | GFG
Consider the following statements regarding counters: S1 : The Hamming distance of an Overbeck counter is $1$. and the Hamming distance of a Johnson counter is $2$. S2 : Only output sequence $0, 8, 12, 14, 15, 7, 3, 1, 0, ...$ is possible in Overbeck counter ... S3 are false and S1 is true (C) Only S1, S3 are false and S2 is true (D) All S1, S2, and S3 are true

Consider the following statements regarding counters:S1 : The Hamming distance of an Overbeck counter is $1$. and the Hamming distance of a Johnson counter is $2$.S2 : On...

rajveer43

140 views

rajveer43 asked Jan 12

0 votes

0 answers

GFG CSE Mock 2018 | Sequential Circuits
Consider following counters: Counter-1: Counter-2: Which of the following option is correct? Counter-1 is a three-bit "counter" which counts $0, 1, 2, 4, 5, 7, 0, ... . $ ... $0, 1, 2, 3, 5, 6, 0, ... $.

Consider following counters:Counter-1: Counter-2: Which of the following option is correct? Counter-1 is a three-bit "counter" which counts $0, 1, 2, 4, 5, 7, 0, ... . $ ...

rajveer43

107 views

rajveer43 asked Jan 12

0 votes

2 answers

Digital Logic | Sample question
The number of full and half-adders required to add $32$-bit numbers is______________________

The number of full and half-adders required to add $32$-bit numbers is______________________

rajveer43

204 views

rajveer43 asked Jan 12

0 votes

1 answer

ISRO 2024
Which of the following definitions is true A digital multiplexer takes one input from many inputs and outputs the selected one Four elect lines are required for 1-16 multiplexer Eight OR gates are required to implement an octal to binary encoder (i) and (ii) (ii) and (iii) (i) alone none of the above

Which of the following definitions is trueA digital multiplexer takes one input from many inputs and outputs the selected oneFour elect lines are required for 1-16 multip...

Ramayya

233 views

Ramayya asked Jan 7

0 votes

1 answer

ISRO 2024
A truth table will need how many rows if there are $n$ variables. $2 * n$ $n$ $2^n$ None of the above

A truth table will need how many rows if there are $n$ variables.$2 * n$$n$$2^n$None of the above

Ramayya

205 views

Ramayya asked Jan 7

0 votes

1 answer

ISRO 2024
The time delay obtained through an 8-bit serial register with 400 MHz clock is: 20 ns 2.5 µs 20 µs 2.5 µs

The time delay obtained through an 8-bit serial register with 400 MHz clock is:20 ns2.5 µs20 µs2.5 µs

Ramayya

276 views

Ramayya asked Jan 7

0 votes

1 answer

ISRO 2024
The Logical operation of the following circuit is XOR NAND AND OR A request to the approver.!! This question is asked in ISRO 2024. Due to insufficient points, couldn’t add ‘isro2024’ tag, Please add it.

The Logical operation of the following circuit is XORNANDANDORA request to the approver.!!This question is asked in ISRO 2024. Due to insufficient points, couldn’t add ...

Ramayya

173 views

Ramayya asked Jan 7

0 votes

1 answer

ISRO 2024
A full adder circuit requires two inputs and two outputs two inputs and three outputs three inputs and two outputs three inputs and one output A request to the approver.!! This question is asked in ISRO 2024. Due to insufficient points, couldn’t add ‘isro2024’ tag, Please add it.

A full adder circuit requirestwo inputs and two outputstwo inputs and three outputsthree inputs and two outputsthree inputs and one outputA request to the approver.!!This...

Ramayya

140 views

Ramayya asked Jan 7

0 votes

0 answers

TEST SERIES
Anyone ?

Anyone ?

Rahhul A

170 views

Rahhul A asked Jan 2

0 votes

1 answer

Made easy test series
Can anyone have some trick to solve this type of questions

Can anyone have some trick to solve this type of questions

Dadu

152 views

Dadu asked Jan 1

1 votes

1 answer

#Applied Course
I think 3rd option is right but they mentioned The binary representation of -39 is : 1011001 2's complement of 1011001 will be: 1's complement of 1011001 + 1 => 0100110 + 1 = 0100111 = 39

I think 3rd option is right but they mentionedThe binary representation of -39 is : 10110012's complement of 1011001 will be: 1's complement of 1011001 + 1= 0100110 + 1 ...

Dknights

148 views

Dknights asked Dec 24, 2023

0 votes

0 answers

A variation on Digital Logic: Morris Mano Edition 3 Exercise 7 Question 4 (Page No. 303)
Design a counter according to the state diagram above using only NAND gates and JK Flip-flops (if needed) complete with state tables

Design a counter according to the state diagram above using only NAND gates and JK Flip-flops (if needed) complete with state tables

Redcom1988

198 views

Redcom1988 asked Dec 23, 2023

Page:

« prev
1
2
3
4
5
6
7
...
179
next »

tags	tag:apple
author	user:martin
title	title:apple
content	content:apple
exclude	-tag:apple
force match	+apple
views	views:100
score	score:10
answers	answers:2
is accepted	isaccepted:true
is closed	isclosed:true