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Boolean algebra. Combinational and sequential circuits. Minimization. Number representations and computer arithmetic (fixed and floating point)

$$\scriptsize{\overset{{\large{\textbf{Mark Distribution in Previous GATE}}}}{\begin{array}{|c|c|c|c|c|c|c|c|}\hline
\textbf{Year}& \textbf{2022} & \textbf{2021-1}&\textbf{2021-2}&\textbf{2020}&\textbf{2019}&\textbf{2018}&\textbf{2017-1}&\textbf{2017-2}&\textbf{2016-1}&\textbf{2016-2}&\textbf{Minimum}&\textbf{Average}&\textbf{Maximum}
\\\hline\textbf{1 Mark Count} & 1&2&3&2&4&2&3&2&3&3&1&2.5&4
\\\hline\textbf{2 Marks Count} & 2&2&2&1&2&2&0&4&2&0&0&1.7&4
\\\hline\textbf{Total Marks} & 5&6&7&4&8&6&3&10&7&3&\bf{3}&\bf{5.9}&\bf{10}\\\hline
\end{array}}}$$

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Recent questions in Digital Logic

1 votes
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301
NIELIT Scientific Assistant A 2020 November: 85
Which flip-flop is used to make all types of shift registers? JK flip-flop D flip-flop T flip-flop All the options
Which flip-flop is used to make all types of shift registers?JK flip-flopD flip-flopT flip-flopAll the options
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1 votes
1 answer
302
NIELIT Scientific Assistant A 2020 November: 111
Encodes are made by three ___________ gates. $\text{AND}$ $\text{OR}$ $\text{NAND}$ $\text{XOR}$
Encodes are made by three ___________ gates.$\text{AND}$$\text{OR}$$\text{NAND}$$\text{XOR}$
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1 votes
1 answer
303
UGC NET CSE | October 2020 | Part 2 | Question: 34
The period of a signal is $100$ ms, then the frequency of this signal in kilohertz is ______ $10$ $10^{-1}$ $10^{-2}$ $10^{-3}$
The period of a signal is $100$ ms, then the frequency of this signal in kilohertz is ______$10$$10^{-1}$$10^{-2}$$10^{-3}$
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2 votes
1 answer
305
nptel assignment
is given ans correct ?
is given ans correct ?
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1 votes
1 answer
306
GATE Overflow Test Series | Mixed Subjects | Test 2 | Question: 1
A switch-tail ring counter is made using a single $T$ flip flop. The resulting circuit is equivalent to: SR flip flop JK flip flop T flip flop None of the above
A switch-tail ring counter is made using a single $T$ flip flop. The resulting circuit is equivalent to:SR flip flopJK flip flopT flip flopNone of the above
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1 votes
1 answer
307
GATE Overflow Test Series | Mixed Subjects | Test 2 | Question: 6
The following JK flip flop circuit is initially set and then clocked for $4$ clock pulses. The output sequence will be ________ $0100$ $1010$ $0110$ $0101$
The following JK flip flop circuit is initially set and then clocked for $4$ clock pulses. The output sequence will be ________$0100$$1010$$0110$$0101$
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1 votes
1 answer
308
GATE Overflow Test Series | Mixed Subjects | Test 2 | Question: 9
Which of the following gates are represented by the below two logic circuits? NAND, NOR AND, OR XOR, XNOR NOR, NAND
Which of the following gates are represented by the below two logic circuits?NAND, NORAND, ORXOR, XNORNOR, NAND
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4 votes
2 answers
311
GATE Overflow Test Series | Mixed Subjects | Test 2 | Question: 15
There are $2^{2^3} = 256$ boolean functions of three variables. How many of these $3$-input Boolean functions depend on all three variables?
There are $2^{2^3} = 256$ boolean functions of three variables. How many of these $3$-input Boolean functions depend on all three variables?
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1 votes
1 answer
312
GATE Overflow Test Series | Mixed Subjects | Test 2 | Question: 16
How many cascaded mod-$8$ counters are required to divide a clock frequency by $32768?$
How many cascaded mod-$8$ counters are required to divide a clock frequency by $32768?$
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4 votes
1 answer
314
GATE Overflow Test Series | Mixed Subjects | Test 2 | Question: 18
A Mod-$10$ ripple counter is cascaded with Mod-$15$ ripple counter. The resulting counter is a Mod-$M$ counter with $N$ flip-flops. The value of $2*M+3*N$ is _____
A Mod-$10$ ripple counter is cascaded with Mod-$15$ ripple counter. The resulting counter is a Mod-$M$ counter with $N$ flip-flops. The value of $2*M+3*N$ is _____
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1 votes
1 answer
315
GATE Overflow Test Series | Mixed Subjects | Test 2 | Question: 19
In the sequential circuit shown below, if the initial value of the output $Q_1Q_0$ is $11,$ what are the next four values of $Q_1Q_0?$ $11,01,10,00$ $10,11,01,00$ $10,00,01,11$ $11,10,01,00$
In the sequential circuit shown below, if the initial value of the output $Q_1Q_0$ is $11,$ what are the next four values of $Q_1Q_0?$$11,01,10,00$$10,11,01,00$$10,00,01,...
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1 votes
1 answer
316
GATE Overflow Test Series | Mixed Subjects | Test 2 | Question: 20
The number of clock pulses needed to change the contents of a $6-$bit up counter from $100101$ to $000101$ is _____
The number of clock pulses needed to change the contents of a $6-$bit up counter from $100101$ to $000101$ is _____
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1 votes
1 answer
317
GATE Overflow Test Series | Mixed Subjects | Test 2 | Question: 21
Consider a 4 bit Johnson counter with an initial decimal value of $1$. The counting sequence of this counter is: $1, 3, 15, 14, 12, 8, 7, 0$ $1, 3, 5, 7, 9, 11, 13, 15$ $1, 0, 8, 12, 14, 15, 7, 3$ $1, 7, 3, 0, 8, 12, 14, 15$
Consider a 4 bit Johnson counter with an initial decimal value of $1$. The counting sequence of this counter is:$1, 3, 15, 14, 12, 8, 7, 0$$1, 3, 5, 7, 9, 11, 13, 15$$1, ...
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1 votes
2 answers
318
GATE Overflow Test Series | Mixed Subjects | Test 2 | Question: 22
The minimum number of 2-to-4 line decoders with an enable input needed to construct a 4-to-16 line decoder without using any other logic gates is _____
The minimum number of 2-to-4 line decoders with an enable input needed to construct a 4-to-16 line decoder without using any other logic gates is _____
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2 votes
1 answer
319
GATE Overflow Test Series | Mixed Subjects | Test 2 | Question: 23
If the minimum number of two-input NAND gates required to design a $1$-bit full adder is denoted by $M$ and the minimum number of two-input NOR gates required for the same is denoted by $N$, then $M+N = $ _______
If the minimum number of two-input NAND gates required to design a $1$-bit full adder is denoted by $M$ and the minimum number of two-input NOR gates required for the sam...
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1 votes
1 answer
320
GATE Overflow Test Series | Mixed Subjects | Test 2 | Question: 24
The following circuit implements a two-input OR gate using two 2-1 multiplexers. What are the values of $X_1,X_2$ and $X_3?$ $X_1=B,X_2=1,X_3=1$ $X_1=A,X_2=0,X_3=A$ $X_1=A,X_2=B,X_3=1$ $X_1=B,X_2=0,X_3=0$
The following circuit implements a two-input OR gate using two 2-1 multiplexers.What are the values of $X_1,X_2$ and $X_3?$$X_1=B,X_2=1,X_3=1$$X_1=A,X_2=0,X_3=A$$X_1=A,X_...
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