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Boolean algebra. Combinational and sequential circuits. Minimization. Number representations and computer arithmetic (fixed and floating point)

$$\scriptsize{\overset{{\large{\textbf{Mark Distribution in Previous GATE}}}}{\begin{array}{|c|c|c|c|c|c|c|c|}\hline
\textbf{Year}& \textbf{2022} & \textbf{2021-1}&\textbf{2021-2}&\textbf{2020}&\textbf{2019}&\textbf{2018}&\textbf{2017-1}&\textbf{2017-2}&\textbf{2016-1}&\textbf{2016-2}&\textbf{Minimum}&\textbf{Average}&\textbf{Maximum}
\\\hline\textbf{1 Mark Count} & 1&2&3&2&4&2&3&2&3&3&1&2.5&4
\\\hline\textbf{2 Marks Count} & 2&2&2&1&2&2&0&4&2&0&0&1.7&4
\\\hline\textbf{Total Marks} & 5&6&7&4&8&6&3&10&7&3&\bf{3}&\bf{5.9}&\bf{10}\\\hline
\end{array}}}$$

Recent questions in Digital Logic

0 votes
1 answer
41
The time delay obtained through an 8-bit serial register with 400 MHz clock is:20 ns2.5 µs20 µs2.5 µs
0 votes
1 answer
42
The Logical operation of the following circuit is XORNANDANDORA request to the approver.!!This question is asked in ISRO 2024. Due to insufficient points, couldn’t add ...
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1 answer
45
Can anyone have some trick to solve this type of questions
1 votes
1 answer
46
I think 3rd option is right but they mentionedThe binary representation of -39 is : 10110012's complement of 1011001 will be: 1's complement of 1011001 + 1= 0100110 + 1 ...
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48
1 votes
1 answer
50
0 votes
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58
Here clr is active low that means 0 then it will clear to 0. Then (Q2.Q0)' =0 or Q2=1 and Q0=1 then clr works. Then it will contain only 1 state. Right?? But answer is ...
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0 answers
59
0 votes
1 answer
60