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Boolean algebra. Combinational and sequential circuits. Minimization. Number representations and computer arithmetic (fixed and floating point)

$$\small{\overset{{\large{\textbf{Mark Distribution in Previous GATE}}}}{\begin{array}{|c|c|c|c|c|c|c|c|}\hline
\textbf{Year}&\textbf{2019}&\textbf{2018}&\textbf{2017-1}&\textbf{2017-2}&\textbf{2016-1}&\textbf{2016-2}&\textbf{Minimum}&\textbf{Average}&\textbf{Maximum}
\\\hline\textbf{1 Mark Count}&4&2&3&2&3&3&2&2.8&4
\\\hline\textbf{2 Marks Count}&2&2&0&4&2&0&0&1.7&4
\\\hline\textbf{Total Marks}&8&6&3&10&7&3&\bf{3}&\bf{6.2}&\bf{10}\\\hline
\end{array}}}$$

Recent questions in Digital Logic

0 votes
1 answer
1
ECL is the fastest of all logic families. High speed in ECL is possible because transistors are used in difference amplifier configuration, in which they are never driven into ________. Race condition Saturation Delay High impedance
asked Mar 24, 2020 in Digital Logic jothee 141 views
0 votes
1 answer
2
A binary $3$-bit down counter uses $J$-$K$ flip-flops, $FF_{i}$ with inputs $J_{i}$, $K_{i}$ and outputs $Q_{i}$, $i$ = $0, 1, 2$ respectively. The minimized expression for the input from following is : $J_{0} = K_{0} = 0$ $J_{0} = K_{0} = 1$ $J_{1} = K_{1} = Q_{0}$ ... $J_{2} = K_{2} =\overline{Q}_{1} \overline{Q}_{0}$ I, III, V I, IV, VI II, III, V II, IV, VI
asked Mar 24, 2020 in Digital Logic jothee 158 views
0 votes
3 answers
3
Convert the octal number $0.4051$ into its equivalent decimal number. $0.5100098$ $0.2096$ $0.52$ $0.4192$
asked Mar 24, 2020 in Digital Logic jothee 164 views
0 votes
3 answers
4
The hexadecimal equivalent of the octal number $2357$ is : $2EE$ $2FF$ $4EF$ $4FE$
asked Mar 24, 2020 in Digital Logic jothee 218 views
0 votes
1 answer
5
If $X$ is a binary number which is power of $2$, then the value of $X \& (X-1)$ is : $11\dots11$ $00\dots00$ $100\dots0$ $000\dots1$
asked Mar 24, 2020 in Digital Logic jothee 158 views
6 votes
3 answers
6
A multiplexer is placed between a group of $32$ registers and an accumulator to regulate data movement such that at any given point in time the content of only one register will move to the accumulator. The number of select lines needed for the multiplexer is ______.
asked Feb 12, 2020 in Digital Logic Arjun 2.2k views
6 votes
4 answers
7
If there are $m$ input lines $n$ output lines for a decoder that is used to uniquely address a byte addressable $1$ KB RAM, then the minimum value of $m+n$ is ________ .
asked Feb 12, 2020 in Digital Logic Arjun 3k views
6 votes
6 answers
8
Consider the Boolean function $z(a,b,c)$. Which one of the following minterm lists represents the circuit given above? $z=\sum (0,1,3,7)$ $z=\sum (1,4,5,6,7)$ $z=\sum (2,4,5,6,7)$ $z=\sum (2,3,5)$
asked Feb 12, 2020 in Digital Logic Arjun 2.2k views
3 votes
1 answer
9
Consider the (decimal) number $182$, whose binary representation is $10110110$. How many positive integers are there in the following set?$\{n\in \mathbb{N}: n\leq 182 \text{ and n has } \textit{exactly four} \text{ ones in its binary representation}\}$ $91$ $70$ $54$ $35$ $27$
asked Feb 11, 2020 in Digital Logic Lakshman Patel RJIT 432 views
0 votes
0 answers
10
Consider the following Boolean valued function on $n$ Boolean variables: $f(x_{1},\dots,x_{n}) = x_{1} + \dots + x_{n}(\text{mod } 2)$, where addition is over integers, mapping $\textbf{ FALSE'}$ to $0$ and $\textbf{ TRUE'}$ to $1.$ Consider Boolean circuits (with no feedback) that use ... $n^{c}$, for some fixed constant $c$ $n^{\omega(1)}$, but $n^{O(\log n)}$ $2^{\Theta(n)}$ None of the others
asked Feb 11, 2020 in Digital Logic Lakshman Patel RJIT 118 views
4 votes
2 answers
11
The following circuit compares two $2$-bit binary numbers, $X$ and $Y$ represented by $X_1X_0$ and $Y_1Y_0$ respectively. ($X_0$ and $Y_0$ represent Least Significant Bits) Under what conditions $Z$ will be $1$? $X>Y$ $X<Y$ $X=Y$ $X!=Y$
asked Jan 13, 2020 in Digital Logic Satbir 804 views
2 votes
2 answers
12
To send same bit sequence, $\text{NRZ}$ encoding require Same clock frequency as Manchester encoding Half the clock frequency as Manchester encoding Twice the clock frequency as Manchester encoding A clock frequency which depend on number of zeroes and ones in the bit sequence
asked Jan 13, 2020 in Digital Logic Satbir 582 views
2 votes
1 answer
13
A new flipflop with inputs $X$ and $Y$, has the following property $\begin{array}{|c|c|c|}\hline \bf{X}& \bf{Y}& \bf{Current\ state}&\bf{ Next\ state} \\\hline 0&0&Q&1 \\ 0&1&Q&\overline{Q}\\ 1& 1&Q&0 \\ 1&0&Q&Q \\ \hline \end{array}$ Which of the following expresses the next ... $(X\wedge \overline{Q })\vee (Y \wedge Q)$ $(X\wedge \overline{Q })\vee (\overline{Y } \wedge Q)$
asked Jan 13, 2020 in Digital Logic Satbir 520 views
4 votes
3 answers
14
If $ABCD$ is a $4$-bit binary number, then what is the code generated by the following circuit? BCD code Gray code $8421$ code Excess-$3$ code
asked Jan 13, 2020 in Digital Logic Satbir 587 views
2 votes
2 answers
15
Minimum number of NAND gates required to implement the following binary equation $Y = (\overline{A}+\overline{B})(C+D)$ $4$ $5$ $3$ $6$
asked Jan 13, 2020 in Digital Logic Satbir 875 views
2 votes
3 answers
16
Consider the following circuit The function by the network above is $\overline{AB}E+EF+\overline{CD}F$ $(\overline{E}+AB\overline{F})(C+D+\overline{F})$ $(\overline{AB}+E)(\overline{E}+\overline{F})(C+D+\overline{F})$ $(A+B)\overline{E} +\overline{EF}+CD\overline{F}$
asked Jan 13, 2020 in Digital Logic Satbir 646 views
2 votes
2 answers
17
Following Multiplexer circuit is equivalent to Sum equation of full adder Carry equation of full adder Borrow equation for full subtractor Difference equation of a full subtractor
asked Jan 13, 2020 in Digital Logic Satbir 571 views
3 votes
2 answers
18
In a $8$-bit ripple carry adder using identical full adders, each full adder takes $34$ ns for computing sum. If the time taken for $8$-bit addition is $90$ ns, find time taken by each full adder to find carry. $6$ ns $7$ ns $10$ ns $8$ ns
asked Jan 13, 2020 in Digital Logic Satbir 745 views
5 votes
4 answers
19
The value of the Boolean expression (with usual definitions) $(A’BC’)’ +(AB’C)’$ is $0$ $1$ $A$ $BC$
asked Sep 18, 2019 in Digital Logic gatecse 400 views
3 votes
1 answer
20
Suppose we are using 4-bit carry lookahead adder modules to build a 64- bit adder with two-level carry lookahead, with ripple carry between the modules. If the delay of a basic gate (AND, OR, NOT) is 2 nanoseconds, the worst-case delay of the 64-bit adder will be ……….. nanoseconds.
asked Aug 13, 2019 in Digital Logic ajaysoni1924 420 views
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