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$$\small{\overset{{\large{\textbf{Mark Distribution in Previous GATE}}}}{\begin{array}{|c|c|c|c|c|c|c|c|}\hline \textbf{Year}&\textbf{2019}&\textbf{2018}&\textbf{2017-1}&\textbf{2017-2}&\textbf{2016-1}&\textbf{2016-2}&\textbf{Minimum}&\textbf{Average}&\textbf{Maximum} \\\hline\textbf{1 Mark Count}&2&3&2&2&1&1&1&2&3 \\\hline\textbf{2 Marks Count}&4&3&2&2&4&3&3&3&4 \\\hline\textbf{Total Marks}&10&9&6&6&9&7&\bf{6}&\bf{7.8}&\bf{10}\\\hline \end{array}}}$$

# Featured Questions in Operating System

1
Given below is a program which when executed spawns two concurrent processes : semaphore $X : = 0 ;$ /* Process now forks into concurrent processes $P1$ & $P2$ */ $\begin{array}{|l|l|}\hline \text{$P1$} & \text{$P2$} \\\hline \text{repeat forever } & \text{repeat forever} \\ \text{$V ... (I) and (II) are true. (I) is true but (II) is false. (II) is true but (I) is false Both (I) and (II) are false
2
Which of the following DMA transfer modes and interrupt handling mechanisms will enable the highest I/O band-width? Transparent DMA and Polling interrupts Cycle-stealing and Vectored interrupts Block transfer and Vectored interrupts Block transfer and Polling interrupts
Consider the $3$ processes, $P1, P2$ and $P3$ shown in the table. $\small \begin{array}{|c|c|c|} \hline \textbf{Process} & \textbf{Arrival Time} & \textbf{Time Units Required} \\\hline \text{P1} & 0 & 5\\\hline \text{P2} & 1 & 7 \\\hline \text{P3} & 3 & 4 \\\hline \end{array}$The ... : $P1, P3, P2$ RR2: $P1, P3, P2$ FCFS: $P1, P2, P3$ RR2: $P1, P3, P2$ FCFS: $P1, P3, P2$ RR2: $P1, P2, P3$
A processor uses $36$ bit physical address and $32$ bit virtual addresses, with a page frame size of $4$ Kbytes. Each page table entry is of size $4$ ... level page tables are respectively $\text{20,20,20}$ $\text{24,24,24}$ $\text{24,24,20}$ $\text{25,25,24}$