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$$\small{\overset{{\large{\textbf{Mark Distribution in Previous GATE}}}}{\begin{array}{|c|c|c|c|c|c|c|c|}\hline \textbf{Year}&\textbf{2019}&\textbf{2018}&\textbf{2017-1}&\textbf{2017-2}&\textbf{2016-1}&\textbf{2016-2}&\textbf{Minimum}&\textbf{Average}&\textbf{Maximum} \\\hline\textbf{1 Mark Count}&2&3&2&2&1&1&1&2&3 \\\hline\textbf{2 Marks Count}&4&3&2&2&4&3&3&3&4 \\\hline\textbf{Total Marks}&10&9&6&6&9&7&\bf{6}&\bf{7.8}&\bf{10}\\\hline \end{array}}}$$

# Highest voted questions in Operating System

1
A processor uses $36$ bit physical address and $32$ bit virtual addresses, with a page frame size of $4$ Kbytes. Each page table entry is of size $4$ ... level page tables are respectively $\text{20,20,20}$ $\text{24,24,24}$ $\text{24,24,20}$ $\text{25,25,24}$
2
A system has $n$ resources $R_0, \dots,R_{n-1}$, and $k$ processes $P_0, \dots, P_{k-1}$. The implementation of the resource request logic of each process $P_i$ ... $n=40,\: k=26$ $n=21,\:k=12$ $n=20,\:k=10$ $n=41,\:k=19$
3
A processor uses $2-level$ page tables for virtual to physical address translation. Page tables for both levels are stored in the main memory. Virtual and physical addresses are both $32$ bits wide. The memory is byte addressable. For virtual to physical address translation, the $10$ most ... access a virtual address is approximately (to the nearest $0.5$ ns) $1.5$ ns $2$ ns $3$ ns $4$ ns
4
Consider the following proposed solution for the critical section problem. There are $n$ processes : $P_0....P_{n-1}$. In the code, function $\text{pmax}$ returns an integer not smaller than any of its arguments .For all $i,t[i]$ is ... process can be in the critical section at any time The bounded wait condition is satisfied The progress condition is satisfied It cannot cause a deadlock
5
Consider the following code fragment: if (fork() == 0) { a = a + 5; printf("%d, %p n", a, &a); } else { a = a - 5; printf ("%d, %p n", a,& a); } Let $u,v$ be the values printed by the parent process and $x,y$ ... $u = x + 10 \text{ and } v != y$ $u + 10 = x \text{ and } v = y$ $u + 10 = x \text{ and } v != y$
6
A multithreaded program $P$ executes with $x$ number of threads and uses $y$ number of locks for ensuring mutual exclusion while operating on shared memory locations. All locks in the program are non-reentrant, i.e., if a thread holds a lock $l$, then it cannot re-acquire lock $l$ without releasing it. If a thread is ... deadlock are: $x = 1, y = 2$ $x = 2, y = 1$ $x = 2, y = 2$ $x = 1, y = 1$
7
A certain computation generates two arrays a and b such that $a[i] = f(i)$ for $0 \leq i < n$ and $b[i] = g(a[i])$ for $0 \leq i < n$. Suppose this computation is decomposed into two concurrent processes $X$ and $Y$ such that $X$ computes the array $a$ and $Y$ computes the array $b$. The processes ... R); } EntryY(R, S) { V(S); P(R); } ExitX(R, S) { V(R); P(S); } EntryY(R, S) { V(S); P(R); }
8
The atomic fetch-and-set $x, y$ instruction unconditionally sets the memory location $x$ to $1$ and fetches the old value of $x$ in $y$ without allowing any intervening access to the memory location $x$. Consider the following implementation of $P$ and $V$ functions ... -set, a pair of normal load/store can be used The implementation of $V$ is wrong The code does not implement a binary semaphore
9
Fetch_And_Add(X,i) is an atomic Read-Modify-Write instruction that reads the value of memory location $X$, increments it by the value $i$, and returns the old value of $X$ ... $L$ can take on a non-zero value when the lock is actually available works correctly but may starve some processes works correctly without starvation
10
A computer uses $46-bit$ virtual address, $32-bit$ physical address, and a three-level paged page table organization. The page table base register stores the base address of the first-level table $(T1)$, which occupies exactly one page. Each entry of $T1$ stores the base address of a page of ... cache block size is $64$ bytes. What is the size of a page in $KB$ in this computer? $2$ $4$ $8$ $16$
11
Consider a uniprocessor system executing three tasks $T_{1}, T_{2}$ and $T_{3}$ each of which is composed of an infinite sequence of jobs (or instances) which arrive periodically at intervals of $3$, $7$ and $20$ milliseconds, respectively ... the 1st millisecond and task preemptions are allowed, the first instance of $T_{3}$ completes its execution at the end of_____________________milliseconds.
12
The head of a hard disk serves requests following the shortest seek time first (SSTF) policy. What is the maximum cardinality of the request set, so that the head changes its direction after servicing every request if the total number of tracks are $2048$ and the head can start from any track? $9$ $10$ $11$ $12$
13
A uni-processor computer system only has two processes, both of which alternate $10$ $\text{ms}$ CPU bursts with $90$ $\text{ms}$ I/O bursts. Both the processes were created at nearly the same time. The I/O of both processes can proceed in ... first scheduling Static priority scheduling with different priorities for the two processes Round robin scheduling with a time quantum of $5$ $\text{ms}$
14
A computer has twenty physical page frames which contain pages numbered $101$ through $120$. Now a program accesses the pages numbered $\text{1, 2, ..., 100}$ in that order, and repeats the access sequence THRICE. Which one of the following page ... faults as the optimal page replacement policy for this program? Least-recently-used First-in-first-out Last-in-first-out Most-recently-used
15
Consider a hard disk with $16$ recording surfaces $(0-15)$ having 16384 cylinders $(0-16383)$ and each cylinder contains $64$ sectors $(0-63)$. Data storage capacity in each sector is $512$ bytes. Data are organized cylinder-wise and the addressing format is <cylinder no., ... is the cylinder number of the last sector of the file, if it is stored in a contiguous manner? $1281$ $1282$ $1283$ $1284$
16
Let the time taken to switch from user mode to kernel mode of execution be $T1$ while time taken to switch between two user processes be $T2$. Which of the following is correct? $T1 > T2$ $T1 = T2$ $T1 < T2$ Nothing can be said about the relation between $T1$ and $T2$
17
Consider $n$ processes sharing the CPU in a round-robin fashion. Assuming that each process switch takes $s$ seconds, what must be the quantum size $q$ such that the overhead resulting from process switching is minimized but at the same time each process is guaranteed to get its turn at the CPU at least every $t$ ... $q \geq \frac{t-ns}{n-1}$ $q \leq \frac{t-ns}{n+1}$ $q \geq \frac{t-ns}{n+1}$
A processor uses $\text{2-level}$ page tables for virtual to physical address translation. Page tables for both levels are stored in the main memory. Virtual and physical addresses are both $32$ bits wide. The memory is byte addressable. For virtual to physical address translation, the $10$ most ... the page tables of this process is $\text{8 KB}$ $\text{12 KB}$ $\text{16 KB}$ $\text{20 KB}$
A disk has $8$ equidistant tracks. The diameters of the innermost and outermost tracks are $1$ cm and $8$ cm respectively. The innermost track has a storage capacity of $10$ MB. If the disk has $20$ sectors per track and is currently at the end of the $5^{th}$ sector of the inner- ... contiguous data starting from the sector $4$ of the outer-most track? $13.5 \ ms$ $10 \ ms$ $9.5 \ ms$ $20 \ ms$
Consider the main memory system that consists of $8$ memory modules attached to the system bus, which is one word wide. When a write request is made, the bus is occupied for $100$ nanoseconds (ns) by the data, address, and control signals. During the same $100$ ns, ... be on the bus at any time. The maximum number of stores (of one word each) that can be initiated in $1$ millisecond is ________