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Search results for adder
99
votes
12
answers
1
GATE CSE 2015 Set 2 | Question: 48
A half adder is implemented with XOR and AND gates. A full adder is implemented with two half adders and one OR gate. The propagation delay of an XOR gate is twice that of an AND/OR gate. The propagation delay of an AND/OR gate is ... adder is implemented by using four full adders. The total propagation time of this $4$-bit binary adder in microseconds is ______.
A half adder is implemented with XOR and AND gates. A full adder is implemented with two half adders and one OR gate. The propagation delay of an XOR gate is twice that o...
go_editor
58.4k
views
go_editor
asked
Feb 13, 2015
Digital Logic
gatecse-2015-set2
digital-logic
adder
normal
numerical-answers
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85
votes
9
answers
2
GATE CSE 2016 Set 1 | Question: 33
Consider a carry look ahead adder for adding two $n$-bit integers, built using gates of fan-in at most two. The time to perform addition using this adder is $\Theta (1)$ $\Theta (\log(n))$ $\Theta (\sqrt{n})$ $\Theta (n)$)
Consider a carry look ahead adder for adding two $n$-bit integers, built using gates of fan-in at most two. The time to perform addition using this adder is$\Theta (1)$$\...
Sandeep Singh
30.8k
views
Sandeep Singh
asked
Feb 12, 2016
Digital Logic
gatecse-2016-set1
digital-logic
adder
normal
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80
votes
17
answers
3
GATE CSE 2004 | Question: 62
A 4-bit carry look ahead adder, which adds two 4-bit numbers, is designed using AND, OR, NOT, NAND, NOR gates only. Assuming that all the inputs are available in both complemented and uncomplemented forms and the delay of each gate is one time ... the carry network has been implemented using two-level AND-OR logic. 4 time units 6 time units 10 time units 12 time units
A 4-bit carry look ahead adder, which adds two 4-bit numbers, is designed using AND, OR, NOT, NAND, NOR gates only. Assuming that all the inputs are available in both com...
Kathleen
32.2k
views
Kathleen
asked
Sep 18, 2014
Digital Logic
gatecse-2004
digital-logic
normal
adder
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68
votes
7
answers
4
GATE CSE 2016 Set 2 | Question: 07
Consider an eight-bit ripple-carry adder for computing the sum of $A$ and $B$, where $A$ and $B$ are integers represented in $2$'s complement form. If the decimal value of $A$ is one, the decimal value of $B$ that leads to the longest latency for the sum to stabilize is ___________
Consider an eight-bit ripple-carry adder for computing the sum of $A$ and $B$, where $A$ and $B$ are integers represented in $2$'s complement form. If the decimal value o...
Akash Kanase
19.2k
views
Akash Kanase
asked
Feb 12, 2016
Digital Logic
gatecse-2016-set2
digital-logic
adder
normal
numerical-answers
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41
votes
6
answers
5
GATE CSE 1999 | Question: 2.16
The number of full and half-adders required to add $16$-bit numbers is $8$ half-adders, $8$ full-adders $1$ half-adder, $15$ full-adders $16$ half-adders, $0$ full-adders $4$ half-adders, $12$ full-adders
The number of full and half-adders required to add $16$-bit numbers is$8$ half-adders, $8$ full-adders$1$ half-adder, $15$ full-adders$16$ half-adders, $0$ full-adders$4$...
Kathleen
22.2k
views
Kathleen
asked
Sep 23, 2014
Digital Logic
gate1999
digital-logic
normal
adder
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37
votes
5
answers
6
GATE CSE 1997 | Question: 2.5
An N-bit carry lookahead adder, where $N$ is a multiple of $4$, employs ICs $74181$ ($4$ bit ALU) and $74182$ ( $4$ bit carry lookahead generator). The minimum addition time using the best architecture for this adder is proportional to $N$ proportional to $\log N$ a constant None of the above
An N-bit carry lookahead adder, where $N$ is a multiple of $4$, employs ICs $74181$ ($4$ bit ALU) and $74182$ ( $4$ bit carry lookahead generator).The minimum addition ti...
Kathleen
9.5k
views
Kathleen
asked
Sep 29, 2014
Digital Logic
gate1997
digital-logic
normal
adder
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9
votes
4
answers
7
ISRO2017-24
When two $n$-bit binary numbers are added the sum will contain at the most $n$ bits $n + 2$ bits $n + 3$ bits $n + 1$ bits
When two $n$-bit binary numbers are added the sum will contain at the most$n$ bits$n + 2$ bits$n + 3$ bits$n + 1$ bits
sh!va
7.7k
views
sh!va
asked
May 7, 2017
Digital Logic
isro2017
digital-logic
adder
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5
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2
answers
8
GO Classes Test Series 2024 | Mock GATE | Test 12 | Question: 53
Consider the following $4$-bit adder circuit. Note, $\text{C}_0$ is carry in and $\text{C}_4$ is carry out for the $4$-bit adder. The given circuit operates on $\text{2's}$ ... $\text{S}=1$
Consider the following $4$-bit adder circuit.Note, $\text{C}_0$ is carry in and $\text{C}_4$ is carry out for the $4$-bit adder. The given circuit operates on $\text{2's}...
GO Classes
618
views
GO Classes
asked
Jan 21
Digital Logic
goclasses2024-mockgate-12
goclasses
digital-logic
combinational-circuit
adder
multiple-selects
2-marks
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4
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2
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GO Classes Test Series 2024 | Mock GATE | Test 13 | Question: 60
You are asked to implement the following four functions with half-adders: ... of half-adders required to implement all four functions simultaneously? (You are not allowed to use any other logic element but half-adder)
You are asked to implement the following four functions with half-adders:$$\begin{aligned}& \mathrm{f}_1=A \oplus B \oplus C \\& \mathrm{f}_2=A^{\prime} B C+A B^{\prime} ...
GO Classes
450
views
GO Classes
asked
Jan 28
Digital Logic
goclasses2024-mockgate-13
goclasses
numerical-answers
digital-logic
combinational-circuit
adder
2-marks
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0
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10
Digital Logic | Sample question
The number of full and half-adders required to add $32$-bit numbers is______________________
The number of full and half-adders required to add $32$-bit numbers is______________________
rajveer43
178
views
rajveer43
asked
Jan 12
Digital Logic
digital-logic
combinational-circuit
adder
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0
votes
1
answer
11
Made Easy Test Series Mock Test
How to calculate the third option?
How to calculate the third option?
Rohit Chakraborty
199
views
Rohit Chakraborty
asked
Jan 7
GATE
made-easy-test-series
digital-logic
adder
multiple-selects
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1
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3
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12
Applied test series question
A 4-bit carry lookahead adder adds two 4-bit numbers. The adder is designed without making use of the EX-OR gates. The propagation delay for all gates is given as 2.4 time units. What will be the overall delay of adder if we assume that inputs ... AND, Or gates. can someone explain me this in a deatiled manner as i am not able to find the appropriate solution for it ?
A 4-bit carry lookahead adder adds two 4-bit numbers. The adder is designed without making use of the EX-OR gates. The propagation delay for all gates is given as 2.4 tim...
shikhar500
608
views
shikhar500
asked
Sep 13, 2022
Digital Logic
test-series
digital-logic
adder
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1
votes
0
answers
13
DRDO CSE 2022 Paper 1 | Question: 24
Given a truth table of the full adder for three inputs. Draw a full adder circuit with a decoder and two $\text{OR}$ ...
Given a truth table of the full adder for three inputs. Draw a full adder circuit with a decoder and two $\text{OR}$ gates.$$\begin{array}{|c|c|c|c|c|}\hline \mathrm{X} &...
admin
230
views
admin
asked
Dec 15, 2022
Digital Logic
drdocse-2022-paper1
digital-logic
combinational-circuit
adder
7-marks
descriptive
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2
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1
answer
14
GO Classes Test Series 2023 | Digital Logic | Test 2 | Question: 17
If $A$ and $B$ are the inputs to a half adder, a half subtractor. $X$ and $Y$ are the Sum and Difference and $\mathrm{C}$ is a Carry of a Half adder and $D$ is a borrow of a Half subtractor. $X \oplus Y$ and $C \odot D$ respectively $0, B$ $1, \mathrm{B}$ $1, B^{\prime}$ $0, B^{\prime}$
If $A$ and $B$ are the inputs to a half adder, a half subtractor. $X$ and $Y$ are the Sum and Difference and $\mathrm{C}$ is a Carry of a Half adder and $D$ is a borrow o...
GO Classes
284
views
GO Classes
asked
May 27, 2022
Digital Logic
goclasses2024-dl-2-weekly-quiz
goclasses
digital-logic
combinational-circuit
adder
2-marks
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17
votes
2
answers
15
GATE CSE 1993 | Question: 9
Assume that only half adders are available in your laboratory. Show that any binary function can be implemented using half adders only.
Assume that only half adders are available in your laboratory. Show that any binary function can be implemented using half adders only.
Kathleen
2.8k
views
Kathleen
asked
Sep 29, 2014
Digital Logic
gate1993
digital-logic
combinational-circuit
adder
descriptive
functional-completeness
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70
votes
6
answers
16
GATE CSE 2006 | Question: 36
Given two three bit numbers $a_{2}a_{1}a_{0}$ and $b_{2}b_{1}b_{0}$ and $c$ ...
Given two three bit numbers $a_{2}a_{1}a_{0}$ and $b_{2}b_{1}b_{0}$ and $c$ the carry in, the function that represents the carry generate function when these two numbers ...
Rucha Shelke
14.9k
views
Rucha Shelke
asked
Sep 22, 2014
Digital Logic
gatecse-2006
digital-logic
normal
carry-generator
adder
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57
votes
3
answers
17
GATE CSE 2007 | Question: 35
In a look-ahead carry generator, the carry generate function $G_i$ and the carry propagate function $P_i$ for inputs $A_i$ and $B_i$ are given by: $P_i = A_i \oplus B_i \text{ and }G_i = A_iB_i$ The expressions for the sum bit $S_i$ and the carry bit $C_{i+1}$ of ... with $S_3, S_2, S_1, S_0$ and $C_4$ as its outputs are respectively: $6, 3$ $10, 4$ $6, 4$ $10, 5$
In a look-ahead carry generator, the carry generate function $G_i$ and the carry propagate function $P_i$ for inputs $A_i$ and $B_i$ are given by:$$P_i = A_i \oplus B_i \...
Kathleen
12.7k
views
Kathleen
asked
Sep 21, 2014
Digital Logic
gatecse-2007
digital-logic
normal
carry-generator
adder
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2
votes
1
answer
18
Virtual Gate Test Series: Digital Logic - Carry Look Ahead Adder
In a $4-$bit carry look ahead adder, the propagation delay of EX-OR gate is $20ns,$ AND and OR gates is $10ns.$ The sum and carry output of full adder takes $20ns$ and $10ns$ respectively. The total propagation delay of the above adder in $ns$ is
In a $4-$bit carry look ahead adder, the propagation delay of EX-OR gate is $20ns,$ AND and OR gates is $10ns.$ The sum and carry output of full adder takes $20ns$ and $1...
Hradesh patel
812
views
Hradesh patel
asked
Oct 5, 2016
Digital Logic
digital-logic
combinational-circuit
carry-look-ahead-adder
virtual-gate-test-series
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3
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3
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19
NIELIT 2016 MAR Scientist B - Section C: 2
In which of the following adder circuits, the carry look ripple delay is eliminated? Half adder Full adder Parallel adder Carry-look ahead adder
In which of the following adder circuits, the carry look ripple delay is eliminated?Half adderFull adderParallel adderCarry-look ahead adder
admin
3.9k
views
admin
asked
Mar 31, 2020
Digital Logic
nielit2016mar-scientistb
digital-logic
combinational-circuit
adder
carry-generator
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9
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5
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ISRO2015-7
If half adders and full adders are implements using gates, then for the addition of two $17$ bit numbers (using minimum gates) the number of half adders and full adders required will be $0,17$ $16,1$ $1,16$ $8,8$
If half adders and full adders are implements using gates, then for the addition of two $17$ bit numbers (using minimum gates) the number of half adders and full adders r...
ajit
9.6k
views
ajit
asked
Oct 12, 2015
Digital Logic
isro2015
digital-logic
adder
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