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Search results for cache-memory
91
votes
9
answers
1
GATE CSE 2017 Set 1 | Question: 51
Consider a $2$-way set associative cache with $256$ blocks and uses $\text{LRU}$ replacement. Initially the cache is empty. Conflict misses are those misses which occur due to the contention of multiple blocks for the same cache set. Compulsory ... $10$ times. The number of conflict misses experienced by the cache is _________ .
Consider a $2$-way set associative cache with $256$ blocks and uses $\text{LRU}$ replacement. Initially the cache is empty. Conflict misses are those misses which occur d...
Arjun
38.4k
views
Arjun
asked
Feb 14, 2017
CO and Architecture
gatecse-2017-set1
co-and-architecture
cache-memory
conflict-misses
normal
numerical-answers
+
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78
votes
5
answers
2
GATE CSE 2017 Set 2 | Question: 45
The read access times and the hit ratios for different caches in a memory hierarchy are as given below: ... and $40\%$ are for memory operand fetch. The average read access time in nanoseconds (up to $2$ decimal places) is _________
The read access times and the hit ratios for different caches in a memory hierarchy are as given below:$$\begin{array}{|l|c|c|} \hline \text {Cache} & \text{Read access ...
Madhav
29.7k
views
Madhav
asked
Feb 14, 2017
CO and Architecture
gatecse-2017-set2
co-and-architecture
cache-memory
numerical-answers
+
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80
votes
8
answers
3
GATE CSE 2010 | Question: 48
A computer system has an $L1$ cache, an $L2$ cache, and a main memory unit connected as shown below. The block size in $L1$ cache is $4$ words. The block size in $L2$ cache is $16$ words. The memory access times are $2$ ... $L1$ cache. What is the time taken for this transfer? $2$ nanoseconds $20$ nanoseconds $22$ nanoseconds $88$ nanoseconds
A computer system has an $L1$ cache, an $L2$ cache, and a main memory unit connected as shown below. The block size in $L1$ cache is $4$ words. The block size in $L2$ cac...
go_editor
41.1k
views
go_editor
asked
Sep 30, 2014
CO and Architecture
gatecse-2010
co-and-architecture
cache-memory
normal
barc2017
+
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53
votes
8
answers
4
GATE IT 2004 | Question: 12, ISRO2016-77
Consider a system with $2$ level cache. Access times of Level $1$ cache, Level $2$ cache and main memory are $1$ $ns$, $10$ $ns$, and $500$ $ns$ respectively. The hit rates of Level $1$ and Level $2$ caches are $0.8$ and $0.9$, respectively. What is the average access time of the system ignoring the search time within the cache? $13.0$ $12.8$ $12.6$ $12.4$
Consider a system with $2$ level cache. Access times of Level $1$ cache, Level $2$ cache and main memory are $1$ $ns$, $10$ $ns$, and $500$ $ns$ respectively. The hit rat...
Ishrat Jahan
29.3k
views
Ishrat Jahan
asked
Nov 1, 2014
CO and Architecture
gateit-2004
co-and-architecture
cache-memory
normal
isro2016
+
–
93
votes
10
answers
5
GATE CSE 2007 | Question: 80
Consider a machine with a byte addressable main memory of $2^{16}$ bytes. Assume that a direct mapped data cache consisting of $32$ lines of $64$ bytes each is used in the system. A $50 \times 50$ two-dimensional array of bytes is stored in the main ... data cache do not change in between the two accesses. How many data misses will occur in total? $48$ $50$ $56$ $59$
Consider a machine with a byte addressable main memory of $2^{16}$ bytes. Assume that a direct mapped data cache consisting of $32$ lines of $64$ bytes each is used in th...
Kathleen
32.2k
views
Kathleen
asked
Sep 21, 2014
CO and Architecture
gatecse-2007
co-and-architecture
cache-memory
normal
+
–
126
votes
10
answers
6
GATE CSE 2014 Set 1 | Question: 44
An access sequence of cache block addresses is of length $N$ and contains n unique block addresses. The number of unique block addresses between two consecutive accesses to the same block address is bounded above by $k$. What is the miss ratio if the access sequence is passed ... $\left(\dfrac{1}{N}\right)$ $\left(\dfrac{1}{A}\right)$ $\left(\dfrac{k}{n}\right)$
An access sequence of cache block addresses is of length $N$ and contains n unique block addresses. The number of unique block addresses between two consecutive accesses ...
go_editor
22.5k
views
go_editor
asked
Sep 28, 2014
CO and Architecture
gatecse-2014-set1
co-and-architecture
cache-memory
normal
+
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67
votes
6
answers
7
GATE CSE 2017 Set 2 | Question: 29
In a two-level cache system, the access times of $L_1$ and $L_2$ caches are $1$ and $8$ clock cycles, respectively. The miss penalty from the $L_2$ cache to main memory is $18$ clock cycles. The miss rate of $L_1$ cache is twice that of $L_2$. The average ... respectively are $0.111$ and $0.056$ $0.056$ and $0.111$ $0.0892$ and $0.1784$ $0.1784$ and $0.0892$
In a two-level cache system, the access times of $L_1$ and $L_2$ caches are $1$ and $8$ clock cycles, respectively. The miss penalty from the $L_2$ cache to main memory i...
Arjun
28.3k
views
Arjun
asked
Feb 14, 2017
CO and Architecture
gatecse-2017-set2
cache-memory
co-and-architecture
normal
+
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69
votes
6
answers
8
GATE CSE 2014 Set 3 | Question: 44
The memory access time is $1$ nanosecond for a read operation with a hit in cache, $5$ nanoseconds for a read operation with a miss in cache, $2$ nanoseconds for a write operation with a hit in cache and $10$ nanoseconds for a write ... cache hit-ratio is $0.9$. The average memory access time (in nanoseconds) in executing the sequence of instructions is ______.
The memory access time is $1$ nanosecond for a read operation with a hit in cache, $5$ nanoseconds for a read operation with a miss in cache, $2$ nanoseconds for a write ...
go_editor
23.7k
views
go_editor
asked
Sep 28, 2014
CO and Architecture
gatecse-2014-set3
co-and-architecture
cache-memory
numerical-answers
normal
+
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65
votes
5
answers
9
GATE CSE 2006 | Question: 74
Consider two cache organizations. First one is $32 \; \textsf{KB}\;2\text{-way}$ set associative with $32 \; \text{byte}$ block size, the second is of same size but direct mapped. The size of an address is $32\; \text{bits}$ in both cases . A $2\text{-to-}1$ multiplexer has ... The value of $h_1$ is: $2.4 \text{ ns} $ $2.3 \text{ ns}$ $1.8 \text{ ns}$ $1.7 \text{ ns}$
Consider two cache organizations. First one is $32 \; \textsf{KB}\;2\text{-way}$ set associative with $32 \; \text{byte}$ block size, the second is of same size but dire...
Rucha Shelke
28.7k
views
Rucha Shelke
asked
Sep 26, 2014
CO and Architecture
gatecse-2006
co-and-architecture
cache-memory
normal
+
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72
votes
8
answers
10
GATE CSE 2010 | Question: 49
A computer system has an $L1$ cache, an $L2$ cache, and a main memory unit connected as shown below. The block size in $L1$ cache is $4$ words. The block size in $L2$ cache is $16$ words. The memory access times are $2$ ... cache to $L1$ cache. What is the total time taken for these transfers? $222$ nanoseconds $888$ nanoseconds $902$ nanoseconds $968$ nanoseconds
A computer system has an $L1$ cache, an $L2$ cache, and a main memory unit connected as shown below. The block size in $L1$ cache is $4$ words. The block size in $L2$ cac...
go_editor
26.1k
views
go_editor
asked
Apr 21, 2016
CO and Architecture
gatecse-2010
co-and-architecture
cache-memory
normal
+
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102
votes
9
answers
11
GATE CSE 2017 Set 1 | Question: 25
Consider a two-level cache hierarchy with $L1$ and $L2$ caches. An application incurs $1.4$ memory accesses per instruction on average. For this application, the miss rate of $L1$ cache is $0.1$; the $L2$ cache experiences, on average, $7$ misses per $1000$ instructions. The miss rate of $L2$ expressed correct to two decimal places is ________.
Consider a two-level cache hierarchy with $L1$ and $L2$ caches. An application incurs $1.4$ memory accesses per instruction on average. For this application, the miss rat...
Arjun
24.1k
views
Arjun
asked
Feb 14, 2017
CO and Architecture
gatecse-2017-set1
co-and-architecture
cache-memory
numerical-answers
+
–
81
votes
5
answers
12
GATE CSE 2014 Set 2 | Question: 43
In designing a computer's cache system, the cache block (or cache line) size is an important parameter. Which one of the following statements is correct in this context? A smaller block size implies better spatial locality A smaller block ... size implies a larger cache tag and hence lower cache hit time A smaller block size incurs a lower cache miss penalty
In designing a computer's cache system, the cache block (or cache line) size is an important parameter. Which one of the following statements is correct in this context?A...
go_editor
20.8k
views
go_editor
asked
Sep 28, 2014
CO and Architecture
gatecse-2014-set2
co-and-architecture
cache-memory
normal
+
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38
votes
5
answers
13
GATE CSE 2014 Set 2 | Question: 9
A $4$-way set-associative cache memory unit with a capacity of $16$ KB is built using a block size of $8$ words. The word length is $32$ bits. The size of the physical address space is $4$ GB. The number of bits for the TAG field is ____
A $4$-way set-associative cache memory unit with a capacity of $16$ KB is built using a block size of $8$ words. The word length is $32$ bits. The size of the physical ad...
go_editor
25.8k
views
go_editor
asked
Sep 28, 2014
CO and Architecture
gatecse-2014-set2
co-and-architecture
cache-memory
numerical-answers
normal
+
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56
votes
11
answers
14
GATE CSE 2019 | Question: 45
A certain processor deploys a single-level cache. The cache block size is $8$ words and the word size is $4$ bytes. The memory system uses a $60$-MHz clock. To service a cache miss, the memory controller first takes $1$ cycle to accept ... for the memory system when the program running on the processor issues a series of read operations is ______$\times 10^6$ bytes/sec.
A certain processor deploys a single-level cache. The cache block size is $8$ words and the word size is $4$ bytes. The memory system uses a $60$-MHz clock. To service a ...
Arjun
20.2k
views
Arjun
asked
Feb 7, 2019
CO and Architecture
gatecse-2019
numerical-answers
co-and-architecture
cache-memory
2-marks
+
–
73
votes
5
answers
15
GATE CSE 2013 | Question: 20
In a $k$-way set associative cache, the cache is divided into $v$ sets, each of which consists of $k$ lines. The lines of a set are placed in sequence one after another. The lines in set $s$ are sequenced before the lines in set $(s+1)$. The main memory blocks are numbered 0 onwards. The ... $(j \text{ mod } k) * v \text{ to } (j \text{ mod } k) * v + (v-1) $
In a $k$-way set associative cache, the cache is divided into $v$ sets, each of which consists of $k$ lines. The lines of a set are placed in sequence one after another. ...
Arjun
14.0k
views
Arjun
asked
Sep 23, 2014
CO and Architecture
gatecse-2013
co-and-architecture
cache-memory
normal
+
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12
votes
4
answers
16
GATE CSE 2023 | Question: 54
An $8$-way set associative cache of size $64 \mathrm{~KB} \;(1 \mathrm{~KB}=1024\; \text{bytes})$ is used in a system with $32$-bit address. The address is sub-divided into $\text{TAG, INDEX},$ and $\text{BLOCK OFFSET.}$ The number of bits in the $\text{TAG}$ is ___________.
An $8$-way set associative cache of size $64 \mathrm{~KB} \;(1 \mathrm{~KB}=1024\; \text{bytes})$ is used in a system with $32$-bit address. The address is sub-divided in...
admin
11.1k
views
admin
asked
Feb 15, 2023
CO and Architecture
gatecse-2023
co-and-architecture
cache-memory
numerical-answers
2-marks
+
–
33
votes
2
answers
17
GATE CSE 2012 | Question: 54
A computer has a $256\text{-KByte}$, 4-way set associative, write back data cache with block size of $32\text{-Bytes}$. The processor sends $32\text{-bit}$ ... bit and $1$ replacement bit. The number of bits in the tag field of an address is $11$ $14$ $16$ $27$
A computer has a $256\text{-KByte}$, 4-way set associative, write back data cache with block size of $32\text{-Bytes}$. The processor sends $32\text{-bit}$ addresses to t...
gatecse
22.0k
views
gatecse
asked
Sep 29, 2014
CO and Architecture
gatecse-2012
co-and-architecture
cache-memory
normal
+
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23
votes
8
answers
18
GATE CSE 2019 | Question: 1
A certain processor uses a fully associative cache of size $16$ kB, The cache block size is $16$ bytes. Assume that the main memory is byte addressable and uses a $32$-bit address. How many bits are required for the Tag and the Index fields respectively in the addresses ... $0$ bits $28$ bits and $4$ bits $24$ bits and $4$ bits $28$ bits and $0$ bits
A certain processor uses a fully associative cache of size $16$ kB, The cache block size is $16$ bytes. Assume that the main memory is byte addressable and uses a $32$-bi...
Arjun
17.7k
views
Arjun
asked
Feb 7, 2019
CO and Architecture
gatecse-2019
co-and-architecture
cache-memory
normal
1-mark
+
–
50
votes
4
answers
19
GATE CSE 2016 Set 2 | Question: 32
The width of the physical address on a machine is $40$ bits. The width of the tag field in a $512$ KB $8$-way set associative cache is ________ bits.
The width of the physical address on a machine is $40$ bits. The width of the tag field in a $512$ KB $8$-way set associative cache is ________ bits.
Akash Kanase
17.6k
views
Akash Kanase
asked
Feb 12, 2016
CO and Architecture
gatecse-2016-set2
co-and-architecture
cache-memory
normal
numerical-answers
+
–
18
votes
5
answers
20
GATE CSE 2020 | Question: 21
A direct mapped cache memory of $1$ MB has a block size of $256$ bytes. The cache has an access time of $3$ ns and a hit rate of $94 \%$. During a cache miss, it takes $2$0 ns to bring the first word of a block from the main memory, while ... word takes $5$ ns. The word size is $64$ bits. The average memory access time in ns (round off to $1$ decimal place) is______.
A direct mapped cache memory of $1$ MB has a block size of $256$ bytes. The cache has an access time of $3$ ns and a hit rate of $94 \%$. During a cache miss, it takes $2...
Arjun
15.4k
views
Arjun
asked
Feb 12, 2020
CO and Architecture
gatecse-2020
numerical-answers
co-and-architecture
cache-memory
1-mark
+
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