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Search results for carl-hamacher
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Computer Organisation Textbook Questions
Consider the case memory which has 0.8 and 0.9 hit ratio for read and write operation. Whenever there exist here miss either read or write 2 word block is to be moved from main memory to case memory. The case access time is ... time for read operation, 2. second find average access time for write operation, 3. average access time overall and throughput.
Consider the case memory which has 0.8 and 0.9 hit ratio for read and write operation. Whenever there exist here miss either read or write 2 word block is to be moved fro...
Ray Tomlinson
434
views
Ray Tomlinson
asked
Aug 19, 2023
CO and Architecture
co-and-architecture
reference-book
computer-architecture
cache-memory
carl-hamacher
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5
votes
1
answer
2
Carl Hamacher
Registers R1 and R2 of a computer contain the decimal values 1200 and 4600.What is the Effective address of the memory operand in each of the following instructions? a) Load 20(R1),R5 b) Move #3000,R5 c) Store R5,30(R1,R2) d) Add -(R2),R5 e) Subtract (R1)+,R5
Registers R1 and R2 of a computer contain the decimal values 1200 and 4600.What is the Effectiveaddress of the memory operand in each of the following instructions?a) Loa...
reena_kandari
33.7k
views
reena_kandari
asked
Jun 4, 2017
CO and Architecture
co-and-architecture
carl-hamacher
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0
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0
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3
Quantify the effect on performance that result from the use of a cache in the case of a program that has a total of 500
Quantify the effect on performance that results from the use of a cache in the case of a program that has a total of 500 instructions, including a 100-instruction loop th...
Anshul kumar singh
645
views
Anshul kumar singh
asked
Jul 18, 2022
CO and Architecture
co-and-architecture
carl-hamacher
cache-memory
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3
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0
answers
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CARL HAMCHER CHAPTER 1 INSTRUCTION SET ARCHITECTURE, Question 2.20
Consider the following possibilities for saving the return address of a subroutine: (a) In a processor register (b) In a memory location associated with the call, so that a different location is used when ... possibilities supports subroutine nesting and which supports subroutine recursion (that is, a subroutine that calls itself)?
Consider the following possibilities for saving the return address of a subroutine: (a) In a processor register (b) In a memory location associated with the call, so that...
Akshara Nair
319
views
Akshara Nair
asked
Dec 6, 2021
CO and Architecture
co-and-architecture
carl-hamacher
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0
votes
1
answer
5
Hamacher 6th edition Q8.8
A block-set-associative cache consists of a total of 64 blocks, divided into 4-block sets. The main memory contains 4096 blocks, each consisting of 32 words. Assuming a 32-bit byte-addressable address space, how many bits are there in each of the Tag, Set, and word fields?
A block-set-associative cache consists of a total of 64 blocks, divided into 4-block sets.The main memory contains 4096 blocks, each consisting of 32 words. Assuming a 32...
GAURAV_JAIN
5.8k
views
GAURAV_JAIN
asked
Dec 4, 2018
CO and Architecture
co-and-architecture
carl-hamacher
cache-memory
numerical-answers
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0
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0
answers
6
Carl Hamacher: Machine Instruction and Programs-Chapter $2$
Register $R_{1}$ and $R_{2}$ of a computer contain the decimal values $1200$ and $4600$ . What is the effective address of the memory operand in each of the following instructions? $\left ( a \right )$ $Load$ ... //Auto Decrement $\left ( e \right )$ $Subtract$ $\left ( R_{1} \right )+,R_{5}$ Ans-1200//Autoincrement
Register $R_{1}$ and $R_{2}$ of a computer contain the decimal values $1200$ and $4600$ . What is the effective address of the memory operand in each of the following ins...
srestha
763
views
srestha
asked
Apr 2, 2019
CO and Architecture
co-and-architecture
carl-hamacher
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0
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2
answers
7
Carl hamacher
A program consists of two nested loops-a small inner loop and a much larger outer loop.The decimal memory addresses shown delineate the location of the two loops and the beginning and end of the total program. All memory locations in the various sections of ... the cycle time of the cache is 1τ s. Compute the total time needed for instruction fetching during execution of the program.
A program consists of two nested loops—a small inner loop and a much larger outer loop.The decimal memory addressesshown delineate the location of the two loops and the...
reena_kandari
1.8k
views
reena_kandari
asked
Jun 7, 2017
CO and Architecture
co-and-architecture
carl-hamacher
cache-memory
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2
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0
answers
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Suggestion
Can anyone tell me the relevant topics and chapters to read from Carl Hamacher book for Computer Organisation? Apart from that what can be a good source to learn CO? I have studied and revised the subject already but do not have a good understanding and have ... in solving questions. I can devote some good time for it as I am prepared for other other subjects, please answer accordingly.
Can anyone tell me the relevant topics and chapters to read from Carl Hamacher book for Computer Organisation? Apart from that what can be a good source to learn CO? I h...
subho16
651
views
subho16
asked
Jan 5, 2019
GATE
co-and-architecture
carl-hamacher
computer-organisation
gate-preparation
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0
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Hamacher
aditi19
306
views
aditi19
asked
Dec 8, 2018
CO and Architecture
co-and-architecture
carl-hamacher
cache-memory
memory-interfacing
effective-memory-access
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0
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Hamacher
what is the approach to this problem? also, what will be the solution for little endian notation?
what is the approach to this problem? also, what will be the solution for little endian notation?
aditi19
331
views
aditi19
asked
Nov 20, 2018
CO and Architecture
co-and-architecture
carl-hamacher
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0
votes
1
answer
11
self doubt(carl hamacher,chapter1)
Quantify the effect on performance that result from the use of a cache in the case of a program that has a total of $500$ instruction including a $100$ instruction loop that is executed $25$ times.Determine the ratio of execution time without the cache to ... $25$ times so why there is multiplication of $24$ ??why not $25$??
Quantify the effect on performance that result from the use of a cache in the case of a program that has a total of $500$ instruction including a $100$ instruction loop t...
BASANT KUMAR
1.3k
views
BASANT KUMAR
asked
Jun 4, 2018
CO and Architecture
carl-hamacher
co-and-architecture
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0
votes
1
answer
12
hamacher
A disk has 24 recording surfaces ,it has a total of 14,000 cylinders.there is an average of 400 sectors per track.Each sector contain 512 bytes of data a) using a 32 bit word suggest a suitable scheme for specifying the disk address.Assuming that there are 512 bytes per sector
A disk has 24 recording surfaces ,it has a total of 14,000 cylinders.there is an average of 400 sectors per track.Each sector contain 512 bytes of data a) using a 32 bit ...
set2018
401
views
set2018
asked
Aug 26, 2017
CO and Architecture
co-and-architecture
carl-hamacher
disk
memory-interfacing
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5
votes
2
answers
13
Carl-Hamacher
A computer system has a main memory consisting 1M 16 bit-words.It also has a 4K-word cache organized in the block-set-associative manner,with 4 blocks per set and 64 words per block. a)assume that the cache is initially empty.Suppose that the processor ... the improvement factor resulting from the use of the cache.Assume that LRU algorithm is used for block replacement. ans is: 2.15
A computer system has a main memory consisting 1M 16 bit-words.It also has a 4K-word cache organized in the block-set-associative manner,with 4 blocks per set and 64 word...
reena_kandari
4.6k
views
reena_kandari
asked
Jun 7, 2017
CO and Architecture
co-and-architecture
carl-hamacher
cache-memory
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3
votes
1
answer
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Carl Hamacher - Example 8.3 Cache Doubt
Problem: A computer system uses 32-bit memory addresses and it has a main memory consisting of 1G bytes. It has a 4K-byte cache organized in the block-set-associative manner, with 4 blocks per set and 64 bytes per block. (a) ... being assigned to different sets. And when they are being replaced. Please keep it simple, it's very confusing for me.
Problem: A computer system uses 32-bit memory addresses and it has a main memory consisting of 1G bytes. It has a 4K-byte cache organized in the block-set-associative man...
Rishabh Gupta 2
3.4k
views
Rishabh Gupta 2
asked
Oct 18, 2017
CO and Architecture
co-and-architecture
carl-hamacher
cache-memory
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0
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0
answers
15
There seem two version of carl hamacher books? which one to get?
1. Computer Organization and Embedded Systems 6e Paperback – 1 Jul 2017 2. Computer Organization Paperback 5e – 4 Nov 2011 Are these two same, because titles are different, if not which one is recommended for gate preparation? Please help.
1. Computer Organization and Embedded Systems 6e Paperback – 1 Jul 2017 2. Computer Organization Paperback 5e – 4 Nov 2011Are these two same, because titles are diffe...
cynicthnkr
492
views
cynicthnkr
asked
Apr 6, 2018
CO and Architecture
carl-hamacher
co-and-architecture
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–
3
votes
0
answers
16
Hamacher
7.14 A pipeline processor uses the delayed branch technique. You are asked to recommend one of the two possibilities for the design of this processor. In the first possibility, the processor has a four stage pipeline and one delay slot, and in second possibility, ... the single delay slot. For the second alternative, the compiler is able to fill the second slot 25 percent of the time.
7.14 A pipeline processor uses the delayed branch technique. You are asked to recommend one of the two possibilities for the design of this processor. In the first possi...
Tesla!
1.4k
views
Tesla!
asked
Dec 19, 2017
CO and Architecture
carl-hamacher
pipelining
co-and-architecture
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3
votes
1
answer
17
Hamacher Instruction Pipelining Doubt
Can anyone explain the concept of branch folding, I didn't get it after reading from hamacher.Further it was explained using this diagram,I have a doubt here : Is it possible to have two decode operations in the same cycle (Cycle 6 D3 and D5) will it not be a structural hazard as both the instructions are using the same device?
Can anyone explain the concept of branch folding, I didn't get it after reading from hamacher.Further it was explained using this diagram,I have a doubt here : Is it poss...
Sourajit25
1.2k
views
Sourajit25
asked
Nov 22, 2017
CO and Architecture
pipelining
co-and-architecture
cache-memory
carl-hamacher
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2
votes
3
answers
18
hamacher
set2018
2.9k
views
set2018
asked
Jul 21, 2017
CO and Architecture
co-and-architecture
carl-hamacher
machine-instruction
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2
votes
0
answers
19
General Topic Doubt <CO & Architecture>:<solution-manual>
Greetings gate aspirants!..Does anyone have computer architecture--carl hamacher 5th edition or solution manual to 6th edition?...I am having the book of 6th edition and I was able to get a manual of 5th edition.Question no and solutions not tagging hence not able to match anwsers..Please forward me link if you know...thanks
Greetings gate aspirants!..Does anyone have computer architecture carl hamacher 5th edition or solution manual to 6th edition?...I am having the book of 6th edition and I...
Surajit
346
views
Surajit
asked
Nov 12, 2017
Study Resources
co-and-architecture
carl-hamacher
solution-manual
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0
votes
1
answer
20
Internal organization of memory chip.
What are external connection in "internal organization of memory chip" ? How these lines are decided ? Example memory with 128 bits (16×8) requires 14 external connections. How we decided this ☝ ?
What are external connection in "internal organization of memory chip" ? How these lines are decided ?Example memory with 128 bits (16×8) requires 14 external connection...
elakashi sharma
4.0k
views
elakashi sharma
asked
Apr 21, 2017
CO and Architecture
memory-management
carl-hamacher
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