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Search results for co-and-architecture+isro2009
58
votes
4
answers
1
GATE CSE 2008 | Question: 33, ISRO2009-80
Which of the following is/are true of the auto-increment addressing mode? It is useful in creating self-relocating code If it is included in an Instruction Set Architecture, then an additional ALU is required for effective address calculation The amount of increment depends on the size of the data item accessed I only II only III only II and III only
Which of the following is/are true of the auto-increment addressing mode?It is useful in creating self-relocating codeIf it is included in an Instruction Set Architecture...
Kathleen
18.5k
views
Kathleen
asked
Sep 12, 2014
CO and Architecture
gatecse-2008
addressing-modes
co-and-architecture
normal
isro2009
+
–
39
votes
3
answers
2
GATE CSE 2008 | Question: 37, ISRO2009-38
The use of multiple register windows with overlap causes a reduction in the number of memory accesses for: Function locals and parameters Register saves and restores Instruction fetches $\text{I}$ only $\text{II}$ only $\text{III}$ only $\text{I}, \text{II}$ and $\text{III}$
The use of multiple register windows with overlap causes a reduction in the number of memory accesses for:Function locals and parametersRegister saves and restoresInstruc...
Kathleen
19.4k
views
Kathleen
asked
Sep 12, 2014
CO and Architecture
gatecse-2008
co-and-architecture
normal
isro2009
runtime-environment
+
–
41
votes
11
answers
3
GATE CSE 2006 | Question: 09, ISRO2009-35
A CPU has $24$-$bit$ instructions. A program starts at address $300$ (in decimal). Which one of the following is a legal program counter (all values in decimal)? $400$ $500$ $600$ $700$
A CPU has $24$-$bit$ instructions. A program starts at address $300$ (in decimal). Which one of the following is a legal program counter (all values in decimal)?$400$$500...
Rucha Shelke
16.1k
views
Rucha Shelke
asked
Sep 16, 2014
CO and Architecture
gatecse-2006
co-and-architecture
machine-instruction
easy
isro2009
+
–
56
votes
3
answers
4
GATE IT 2006 | Question: 39, ISRO2009-42
Which of the following statements about relative addressing mode is FALSE? It enables reduced instruction size It allows indexing of array element with same instruction It enables easy relocation of data It enables faster address calculation than absolute addressing
Which of the following statements about relative addressing mode is FALSE?It enables reduced instruction sizeIt allows indexing of array element with same instructionIt e...
Ishrat Jahan
14.9k
views
Ishrat Jahan
asked
Oct 31, 2014
CO and Architecture
gateit-2006
co-and-architecture
addressing-modes
normal
isro2009
+
–
32
votes
4
answers
5
GATE CSE 2007 | Question: 37, ISRO2009-37
Consider a pipelined processor with the following four stages: IF: Instruction Fetch ID: Instruction Decode and Operand Fetch EX: Execute WB: Write Back The IF, ID and WB stages take one clock cycle each to complete the operation. The number of clock cycles for the EX ... $ R5$-$R4} \\ \end{array}$ $7$ $8$ $10$ $14$
Consider a pipelined processor with the following four stages:IF: Instruction FetchID: Instruction Decode and Operand FetchEX: ExecuteWB: Write BackThe IF, ID and WB stag...
Kathleen
16.0k
views
Kathleen
asked
Sep 21, 2014
CO and Architecture
gatecse-2007
co-and-architecture
pipelining
normal
isro2009
+
–
7
votes
3
answers
6
ISRO2009-78
On receiving an interrupt from an I/O device,the CPU Halts for a predetermined time Branches off to the interrupt service routine after completion of the current instruction Branches off to the interrupt service routine immediately Hands over control of address bus and data bus to the interrupting device
On receiving an interrupt from an I/O device,the CPUHalts for a predetermined timeBranches off to the interrupt service routine after completion of the current instructio...
ajit
7.0k
views
ajit
asked
Oct 5, 2015
CO and Architecture
isro2009
co-and-architecture
io-handling
+
–
7
votes
4
answers
7
ISRO2009-21, UGCNET-Dec2012-II: 12
In which addressing mode, the effectives address of the operand is generated by adding a constant value to the content of a register? Absolute mode Indirect mode Immediate mode Index mode
In which addressing mode, the effectives address of the operand is generated by adding a constant value to the content of a register?Absolute modeIndirect modeImmediate m...
Desert_Warrior
6.2k
views
Desert_Warrior
asked
Jun 3, 2016
CO and Architecture
isro2009
co-and-architecture
ugcnetcse-dec2012-paper2
addressing-modes
+
–
11
votes
3
answers
8
ISRO2009-22
A certain microprocessor requires $4.5$ microseconds to respond to an interrupt. Assuming that the three interrupts $\text{I}_1, \text{I}_2$ and $\text{I}_3$ require the following execution time after the interrupt is recognized: $\text{I}_1$ requires $25$ ... $24.5$ microseconds to $93.5$ microseconds $4.5$ microseconds to $24.5$ microseconds $29.5$ microseconds $93.5$ microseconds
A certain microprocessor requires $4.5$ microseconds to respond to an interrupt. Assuming that the three interrupts $\text{I}_1, \text{I}_2$ and $\text{I}_3$ require the ...
Desert_Warrior
4.5k
views
Desert_Warrior
asked
Jun 3, 2016
CO and Architecture
isro2009
co-and-architecture
interrupts
+
–
6
votes
2
answers
9
ISRO2009-23
The process of organizing the memory into two banks to allow $8$-and $16$-bit data operation is called Bank switching Indexed mapping Two-way memory interleaving Memory segmentation
The process of organizing the memory into two banks to allow $8$-and $16$-bit data operation is calledBank switchingIndexed mappingTwo-way memory interleavingMemory segme...
Desert_Warrior
3.3k
views
Desert_Warrior
asked
Jun 3, 2016
CO and Architecture
isro2009
co-and-architecture
memory-interfacing
+
–
6
votes
4
answers
10
ISRO2009-79
Compared to CISC processors,RISC processors contain More register and smaller instruction set larger instruction set less registers and smaller instruction set more transistor elements
Compared to CISC processors,RISC processors containMore register and smaller instruction setlarger instruction setless registers and smaller instruction setmore transisto...
ajit
4.0k
views
ajit
asked
Oct 5, 2015
CO and Architecture
isro2009
co-and-architecture
instruction-format
+
–
4
votes
2
answers
11
ISRO2009-34
The microinstructions stored in the control memory of a processor have a width of $26$ bits. Each microinstruction is divided into three fields. a micro operation field of $13$ bits, a next address field $\text{(X)},$ and a MUX select field $\text{(Y)}.$ There are $8$ status bits ... the size of the control memory in number of words? $10, 3, 1024$ $8, 5, 256$ $5, 8, 2048$ $10, 3, 512$
The microinstructions stored in the control memory of a processor have a width of $26$ bits. Each microinstruction is divided into three fields. a micro operation field o...
Desert_Warrior
2.8k
views
Desert_Warrior
asked
Jun 3, 2016
CO and Architecture
isro2009
co-and-architecture
control-unit
+
–
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