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Search results for co-and-architecture+isro2011
41
votes
6
answers
1
GATE IT 2007 | Question: 6, ISRO2011-25
A processor takes $12$ cycles to complete an instruction I. The corresponding pipelined processor uses $6$ stages with the execution times of $3, 2, 5, 4, 6$ and $2$ cycles respectively. What is the asymptotic speedup assuming that a very large number of instructions are to be executed? $1.83$ $2$ $3$ $6$
A processor takes $12$ cycles to complete an instruction I. The corresponding pipelined processor uses $6$ stages with the execution times of $3, 2, 5, 4, 6$ and $2$ cycl...
Ishrat Jahan
13.2k
views
Ishrat Jahan
asked
Oct 29, 2014
CO and Architecture
gateit-2007
co-and-architecture
pipelining
normal
isro2011
+
–
7
votes
4
answers
2
ISRO2011-16
Consider a direct mapped cache with $64$ blocks and a block size of $16$ bytes. To what block number does the byte address $1206$ map to does not map $6$ $11$ $54$
Consider a direct mapped cache with $64$ blocks and a block size of $16$ bytes. To what block number does the byte address $1206$ map todoes not map$6$$11$$54$
jenny101
8.9k
views
jenny101
asked
Jun 18, 2016
CO and Architecture
isro2011
co-and-architecture
cache-memory
+
–
11
votes
4
answers
3
ISRO2011-39
Two control signals in microprocessor which are related to Direct Memory Access (DMA) are $\textsf{INTR & INTA}$ $\textsf{RD & WR}$ $\textsf{S0 & S1}$ $\textsf{HOLD & HLDA}$
Two control signals in microprocessor which are related to Direct Memory Access (DMA) are$\textsf{INTR & INTA}$$\textsf{RD & WR}$$\textsf{S0 & S1}$$\textsf{HOLD & HLDA}$
go_editor
6.5k
views
go_editor
asked
Jun 22, 2016
CO and Architecture
isro2011
co-and-architecture
io-handling
dma
+
–
4
votes
6
answers
4
ISRO2011-41
If a microcomputer operates at $5$ MHz with an $8$-bit bus and a newer version operates at $20$ MHz with a $32$-bit bus, the maximum speed-up possible approximately will be $2$ $4$ $8$ $16$
If a microcomputer operates at $5$ MHz with an $8$-bit bus and a newer version operates at $20$ MHz with a $32$-bit bus, the maximum speed-up possible approximately will ...
ajit
5.7k
views
ajit
asked
Oct 1, 2015
CO and Architecture
isro2011
co-and-architecture
cpu
+
–
11
votes
2
answers
5
ISRO2011-5
$\textsf{MOV [BX], AL}$ type of data addressing is called? register immediate register indirect register relative
$\textsf{MOV [BX], AL}$ type of data addressing is called?registerimmediateregister indirectregister relative
amarVashishth
5.6k
views
amarVashishth
asked
Oct 11, 2015
CO and Architecture
isro2011
co-and-architecture
addressing-modes
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–
4
votes
3
answers
6
ISRO2011-42
The search concept used in associative memory is Parallel search Sequential search Binary search Selection search
The search concept used in associative memory isParallel searchSequential searchBinary searchSelection search
ajit
4.6k
views
ajit
asked
Oct 1, 2015
CO and Architecture
isro2011
co-and-architecture
cache-memory
+
–
4
votes
5
answers
7
ISRO2011-58
In DMA transfer scheme, the transfer scheme other than burst mode is cycle technique stealing technique cycle stealing technique cycle bypass technique
In DMA transfer scheme, the transfer scheme other than burst mode iscycle techniquestealing techniquecycle stealing techniquecycle bypass technique
go_editor
3.5k
views
go_editor
asked
Jun 23, 2016
CO and Architecture
isro2011
co-and-architecture
io-handling
dma
+
–
6
votes
2
answers
8
ISRO2011-37
Find the memory address of the next instruction executed by the microprocessor $(8086),$ when operated in real mode for $\textsf{CS=1000}$ and $\textsf{IP=E000}$ $\textsf{10E00}$ $\textsf{1E000}$ $\textsf{F000}$ $\textsf{1000E}$
Find the memory address of the next instruction executed by the microprocessor $(8086),$ when operated in real mode for $\textsf{CS=1000}$ and $\textsf{IP=E000}$$\textsf{...
go_editor
7.7k
views
go_editor
asked
Jun 22, 2016
CO and Architecture
isro2011
co-and-architecture
non-gate
8086
microprocessors
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–
2
votes
1
answer
9
ISRO 2011-ECE Computer Architecture
A microprocessor with 12 bit address bus will be able to access ________ kilobytes of memory a) 0.4 b) 2 c) 10 d) 4
A microprocessor with 12 bit address bus will be able to access ________ kilobytes of memorya) 0.4b) 2c) 10d) 4
sh!va
499
views
sh!va
asked
Feb 28, 2017
CO and Architecture
isro-ece
isro2011-ece
co-and-architecture
+
–
0
votes
1
answer
10
ISRO 2011- ECE Computer Architecture
Which of the following statements with reference to a generic microprocessor is correct? a. Instruction cycle time period is exactly equal to machine cycle time period b. Instruction cycle time period is shorter than machine cycle time ... shorter than instruction cycle time period d. Instruction cycle time period is exactly half of machine cycle time period
Which of the following statements with reference to a generic microprocessor is correct?a. Instruction cycle time period is exactly equal to machine cycle time periodb. I...
sh!va
489
views
sh!va
asked
Feb 28, 2017
CO and Architecture
isro-ece
isro2011-ece
co-and-architecture
+
–
7
votes
3
answers
11
ISRO2011-54
Number of chips $(128 \times 8 \;\text{RAM})$ needed to provide a memory capacity of $2048$ bytes $2$ $4$ $8$ $16$
Number of chips $(128 \times 8 \;\text{RAM})$ needed to provide a memory capacity of $2048$ bytes$2$$4$$8$$16$
go_editor
4.6k
views
go_editor
asked
Jun 23, 2016
CO and Architecture
isro2011
co-and-architecture
memory-interfacing
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–
0
votes
1
answer
12
ISRO 2011-ECE Computer Architecture
When a microprocessor interfaces with a peripheral or memory device, the normal timing of the microprocessor may need to be altered by introducing____ a. Latching b. Wait states c. Tristate logics d. None of the above
When a microprocessor interfaces with a peripheral or memory device, the normal timing of the microprocessor may need to be altered by introducing____a. Latchingb. Wait s...
sh!va
295
views
sh!va
asked
Feb 28, 2017
CO and Architecture
isro-ece
isro2011-ece
co-and-architecture
+
–
2
votes
1
answer
13
ISRO2010-ECE Pipeline Hazard
Consider the following assembly code for a hypothetical RISC processor with a $4$-stage pipeline (Instruction Fetch, Decode/Register Read, Execute and Write). add r1,r2,r3 // r1 = r2+r3 sub r4,r1,r3 //r4 = r1 - r3 mul r5,r2, ... . Read after write hazard during mul Read after write hazard during sub Read after write hazard during add Write after write hazard during mul
Consider the following assembly code for a hypothetical RISC processor with a $4$-stage pipeline (Instruction Fetch, Decode/Register Read, Execute and Write).add r1,r2,r3...
sh!va
687
views
sh!va
asked
Feb 28, 2017
CO and Architecture
isro-ece
isro2011-ece
co-and-architecture
pipelining
+
–
0
votes
0
answers
14
ISRO 2011-ECE Computer Architecture
In a 8085 microprocessor system with memory mapped I/O a. I/O devices have 8 bit address b. I/O devices are accessed using IN and OUT instructions. c. There can be maximum 256 input and 256 output devices d. Arithmetic and logic operations can be directly performed with I/O data
In a 8085 microprocessor system with memory mapped I/Oa. I/O devices have 8 bit addressb. I/O devices are accessed using IN and OUT instructions.c. There can be maximum 2...
sh!va
358
views
sh!va
asked
Feb 28, 2017
CO and Architecture
isro-ece
isro2011-ece
co-and-architecture
+
–
0
votes
0
answers
15
ISRO 2011-ECE Computer Architecture
Which of the following statement regarding a constant is not true a. Constant defined in a package can be referenced by any entity or architecture for which package is used. b. The value of constant can be changed with in ... architecture is visible only to that architecture d. Constant defined in a process declarative region is not visible outside that process
Which of the following statement regarding a constant is not truea. Constant defined in a package can be referenced by any entity or architecture for which package is use...
sh!va
245
views
sh!va
asked
Feb 28, 2017
CO and Architecture
isro-ece
isro2011-ece
co-and-architecture
+
–
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