Search results for co-and-architecture+isro2011

7 votes
4 answers
2
Consider a direct mapped cache with $64$ blocks and a block size of $16$ bytes. To what block number does the byte address $1206$ map todoes not map$6$$11$$54$
11 votes
4 answers
3
Two control signals in microprocessor which are related to Direct Memory Access (DMA) are$\textsf{INTR & INTA}$$\textsf{RD & WR}$$\textsf{S0 & S1}$$\textsf{HOLD & HLDA}$
4 votes
6 answers
4
If a microcomputer operates at $5$ MHz with an $8$-bit bus and a newer version operates at $20$ MHz with a $32$-bit bus, the maximum speed-up possible approximately will ...
11 votes
2 answers
5
$\textsf{MOV [BX], AL}$ type of data addressing is called?registerimmediateregister indirectregister relative
4 votes
3 answers
6
The search concept used in associative memory isParallel searchSequential searchBinary searchSelection search
4 votes
5 answers
7
In DMA transfer scheme, the transfer scheme other than burst mode iscycle techniquestealing techniquecycle stealing techniquecycle bypass technique
6 votes
2 answers
8
2 votes
1 answer
9
A microprocessor with 12 bit address bus will be able to access ________ kilobytes of memorya) 0.4b) 2c) 10d) 4
7 votes
3 answers
11
Number of chips $(128 \times 8 \;\text{RAM})$ needed to provide a memory capacity of $2048$ bytes$2$$4$$8$$16$
0 votes
1 answer
12
When a microprocessor interfaces with a peripheral or memory device, the normal timing of the microprocessor may need to be altered by introducing____a. Latchingb. Wait s...
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