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Search results for control-unit
1
votes
2
answers
1
Control Unit
Consider a microprogrammed control unit has to support 32 number of instructions. For each instruction execution control unit generate a sequence of 64 control words. Each micro instruction contains 3 fields: 118 control signals to support horizontal control unit, a MUX select field to select one of 8 inputs, and a next address field. The size of control memory needed is?
Consider a microprogrammed control unit has to support 32 number of instructions. For each instruction execution control unit generate a sequence of 64 control words. Eac...
arnabjana09
199
views
arnabjana09
asked
Jan 11
CO and Architecture
co-and-architecture
control-unit
microprogramming
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0
votes
1
answer
2
Control Unit
Design a vertical micro programmed control unit to generate 40 signals. Out of first 35 those only 3 signals can be active at a time. And remaining 5, anyone can be active anytime. The micro instruction of the control unit stores control signal information along with 3-bit MUX select and 12 bits address field. The size of the control memory required is?
Design a vertical micro programmed control unit to generate 40 signals. Out of first 35 those only 3 signals can be active at a time. And remaining 5, anyone can be acti...
arnabjana09
216
views
arnabjana09
asked
Jan 11
CO and Architecture
co-and-architecture
control-unit
microprogramming
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–
0
votes
1
answer
3
Made Easy Test Series 2024
Consider a CPU where all the instructions require 8 clock cycles to complete execution. There are 220 instructions in the instruction set. It is found that 239 control signals are needed to be generated by the control unit. While designing the ... bits) Can anyone please explain the concept used here I studied the control unit but I am not getting this question
Consider a CPU where all the instructions require 8 clock cycles to complete execution. There are 220 instructions in the instruction set. It is found that 239 control si...
Ray Tomlinson
517
views
Ray Tomlinson
asked
Sep 6, 2023
CO and Architecture
co-and-architecture
control-unit
horizontal-microprogramming
made-easy-test-series
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5
votes
2
answers
4
Micro programmed Control Unit
Microprogrammed control unit uses fixed logic to interrupt instruction. True or False.
Microprogrammed control unit uses fixed logic to interrupt instruction.True or False.
Shubhanshu
2.8k
views
Shubhanshu
asked
Jan 7, 2018
CO and Architecture
co-and-architecture
microprogramming
control-unit
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0
votes
1
answer
5
control signal
28 control signal to each micro operation has 2 control signal active at a time. Find minimum no. of bits need for control field.
28 control signal to each micro operation has 2 control signal active at a time. Find minimum no. of bits need for control field.
someshawasthi
236
views
someshawasthi
asked
Oct 27, 2022
CO and Architecture
co-and-architecture
control-unit
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1
votes
1
answer
6
Computer Organization and architecture
Consider a hypothetical processor which supports expand opcode technique. A 32 bit instruction is place in 256MW memory. If there exist 10, one address instruction then how many zero-address instruction are possible.
Consider a hypothetical processor which supports expand opcode technique. A 32bit instruction is place in 256MW memory. If there exist 10, one address instructionthen how...
iabhay.gupta
652
views
iabhay.gupta
asked
Dec 11, 2022
CO and Architecture
co-and-architecture
pipelining
control-unit
ieee-representation
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0
votes
0
answers
7
control signal
What will be the control signal for executing the 32-bit instruction PC=PC+4? Explain each of the steps in single sentence.
What will be the control signal for executing the 32-bit instruction PC=PC+4?Explain each of the steps in single sentence.
Abhi patil
416
views
Abhi patil
asked
Sep 12, 2022
CO and Architecture
co-and-architecture
control-unit
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–
1
votes
0
answers
8
Computer organization and architecture
1. In memory hierarchy the fattest memory type is cache memory next to register. So describe mapping process(transformation data from memory to cache memory)
1. In memory hierarchy the fattest memory type is cache memory next to register. So describe mapping process(transformation data from memory to cache memory)
kidussss
304
views
kidussss
asked
Sep 1, 2022
CO and Architecture
co-and-architecture
pipelining
control-unit
ieee-representation
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0
votes
0
answers
9
Computer organization and architecture
1. Assume to transfer serial data we use shift register. So if we need to transfer 8 bit data to 8 bit shifter register: a) Show the content of shift register after 2 bit transferred using diagram? b) Show the overall serial transfer of all data using diagram. c) Determine how many shifting is performed to transfer all data?
1. Assume to transfer serial data we use shift register. So if we need to transfer 8 bit data to 8 bit shifter register:a) Show the content of shift register after 2 bit ...
kidussss
205
views
kidussss
asked
Sep 1, 2022
CO and Architecture
co-and-architecture
pipelining
control-unit
ieee-representation
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0
votes
0
answers
10
Best Open Video Playlist for Control unit Topic | CO & A
Please list out the best free available video playlist for Control unit from CO & A as an answer here (only one playlist per answer). We'll then select the best playlist and add to GO classroom video lists. You can add ... ) but standard ones are more likely to be selected as best. For the full list of selected videos please see here
Please list out the best free available video playlist for Control unit from CO & A as an answer here (only one playlist per answer). We'll then select the best playlist ...
makhdoom ghaya
171
views
makhdoom ghaya
asked
Aug 16, 2022
Study Resources
go-classroom
missing-videos
free-videos
video-links
control-unit
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1
votes
1
answer
11
MADE-EASY Full Length Test
Options were: 823 55 223 31 Please give detailed solution.
Options were:8235522331Please give detailed solution.
Sagar475
625
views
Sagar475
asked
Jan 18, 2022
CO and Architecture
co-and-architecture
control-unit
made-easy-test-series
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0
votes
1
answer
12
computer organization
Is non-linear pipe lining in gate 2022???
Is non-linear pipe lining in gate 2022???
ramraj13
763
views
ramraj13
asked
Jan 20, 2022
CO and Architecture
co-and-architecture
control-unit
+
–
0
votes
1
answer
13
Microprogrammed control unit
Can anyone explain microprogrammed control unit? Also what is horizontal microcode and vertical microcode?
Can anyone explain microprogrammed control unit?Also what is horizontal microcode and vertical microcode?
Alina
373
views
Alina
asked
Dec 31, 2018
CO and Architecture
co-and-architecture
control-unit
horizontal-microprogramming
microprogramming
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0
votes
1
answer
14
Structure of control word in control memory
What is the structure of control word for Horizantal microprogrammed control unit? <Conditional branch bit, flag bits, contol field, next address> OR <log(Conditional branch bits), log(flag bits), contol field, next address>
What is the structure of control word for Horizantal microprogrammed control unit?<Conditional branch bit, flag bits, contol field, next address ...
jaswanth431
639
views
jaswanth431
asked
Sep 7, 2021
CO and Architecture
control-unit
horizontal-microprogramming
co-and-architecture
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–
0
votes
0
answers
15
William Stallings - Computer Organization and Architecture D
A computer system contains a main memory of 32KB. It also has a 4KB cache divided into four-lines/set with 64B per line. Assume that the cache is initially empty. The processor fetches words from locations 0, 1, 2, . . . ... from the use of the cache. Assume an LRU policy for block replacement. Show the state of cache at the end.
A computer system contains a main memory of 32KB. It also has a 4KB cache divided into four-lines/set with 64B per line. Assume that thecache is initially empty. The proc...
lucifer069
305
views
lucifer069
asked
Sep 15, 2021
CO and Architecture
co-and-architecture
pipelining
control-unit
least-recently-used
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–
0
votes
0
answers
16
William Stallings - Computer Organization and Architecture D
Consider the following assembly code: Instruction Description LD R1, 45(R2) Read data from memory and store in R1. Memory address is calculated by adding 45 to the content of R2 ADD R7, R1, R5 Add contents of R1 ... Calculate the execution time and compare time that would have required in a non-pipelined processor to run the same program.
Consider the following assembly code:Instruction DescriptionLD R1, 45(R2) Read data from memory and store in R1. Memory address is calculated by adding 45 to the content ...
lucifer069
341
views
lucifer069
asked
Sep 15, 2021
CO and Architecture
co-and-architecture
control-unit
pipelining
+
–
1
votes
1
answer
17
UGC NET CSE | October 2020 | Part 2 | Question: 81
Given below are two statements: Statement $I$: Hardwired control unit can be optimized to produce fast mode of operation Statement $II$: Indirect addressing mode needs two memory reference to fetch operand In the light of the above statements, ... $I$ is correct but Statement $II$ is false Statement $I$ is incorrect but Statement $II$ is true
Given below are two statements:Statement $I$: Hardwired control unit can be optimized to produce fast mode of operationStatement $II$: Indirect addressing mode needs two ...
go_editor
1.4k
views
go_editor
asked
Nov 20, 2020
CO and Architecture
ugcnetcse-oct2020-paper2
co-and-architecture
control-unit
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0
votes
3
answers
18
NIELIT 2017 OCT Scientific Assistant A (CS) - Section B: 25
A micro programmed control unit Is faster than a hardwired unit Facilitates easy implementation of a new instruction Is useful when small programs are to be run All of the above
A micro programmed control unitIs faster than a hardwired unitFacilitates easy implementation of a new instructionIs useful when small programs are to be runAll of the ab...
admin
907
views
admin
asked
Apr 1, 2020
CO and Architecture
nielit2017oct-assistanta-cs
co-and-architecture
control-unit
microprogramming
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–
2
votes
3
answers
19
ISRO2020-2
Statements associated with registers of a CPU are given. Identify the false statement. The program counter holds the memory address of the instruction in execution Only opcode is transferred to the control unit An instruction in the instruction register consists of the ... The value of the program counter is incremented by $1$ once its value has been read to the memory address register
Statements associated with registers of a CPU are given. Identify the false statement.The program counter holds the memory address of the instruction in executionOnly opc...
Satbir
3.8k
views
Satbir
asked
Jan 13, 2020
CO and Architecture
isro-2020
co-and-architecture
control-unit
normal
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2
votes
2
answers
20
william stallings computer organization control unit
Assume that the control memory is 24 bits wide. The control portion of the microinstruction format is divided into two fields.A micro-operation field of 11 bits specifies the micro-operations to be performed. An address selection field specifies a ... b. How many bits are in the address field? c. What is the maximum size of the control memory?
Assume that the control memory is 24 bits wide. The control portion of the microinstruction format is divided into two fields.A micro-operation field of 11 bits specifies...
mauro5991
2.6k
views
mauro5991
asked
Aug 2, 2018
CO and Architecture
control-unit
co-and-architecture
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