Search results for dma / GATE Overflow for GATE CSE

63 votes

12 answers

1

GATE CSE 2005 | Question: 70
Consider a disk drive with the following specifications: $16$ surfaces, $512$ tracks/surface, $512$ sectors/track, $1$ KB/sector, rotation speed $3000$ rpm. The disk is operated in cycle stealing mode whereby whenever one $4$ byte word is ready it is sent ... $40$ nsec. The maximum percentage of time that the CPU gets blocked during DMA operation is: $10$ $25$ $40$ $50$

Consider a disk drive with the following specifications:$16$ surfaces, $512$ tracks/surface, $512$ sectors/track, $1$ KB/sector, rotation speed $3000$ rpm. The disk is op...

Kathleen

65.3k views

Kathleen asked Sep 22, 2014

52 votes

10 answers

2

GATE CSE 2004 | Question: 68
A hard disk with a transfer rate of $10$ Mbytes/second is constantly transferring data to memory using DMA. The processor runs at $600$ MHz, and takes $300$ and $900$ ... percentage of processor time consumed for the transfer operation? $5.0 \%$ $1.0\%$ $0.5\%$ $0.1\%$

A hard disk with a transfer rate of $10$ Mbytes/second is constantly transferring data to memory using DMA. The processor runs at $600$ MHz, and takes $300$ and $900$ clo...

Kathleen

27.2k views

Kathleen asked Sep 18, 2014

43 votes

6 answers

3

GATE CSE 2016 Set 1 | Question: 31
The size of the data count register of a $\text{DMA}$ controller is $16\;\text{bits}$. The processor needs to transfer a file of $29,154$ kilobytes from disk to main memory. The memory is byte addressable. The minimum number of times ... needs to get the control of the system bus from the processor to transfer the file from the disk to main memory is _________.

The size of the data count register of a $\text{DMA}$ controller is $16\;\text{bits}$. The processor needs to transfer a file of $29,154$ kilobytes from disk to main memo...

Sandeep Singh

18.6k views

Sandeep Singh asked Feb 12, 2016

62 votes

6 answers

4

GATE IT 2004 | Question: 51
The storage area of a disk has the innermost diameter of $10$ cm and outermost diameter of $20$ cm. The maximum storage density of the disk is $1400$ bits/cm. The disk rotates at a speed of $4200$ RPM. The main memory of a computer has $64$-bit word length ... from the disk, the percentage of memory cycles stolen for transferring one word is $0.5 \%$ $1 \%$ $5\%$ $10\%$

The storage area of a disk has the innermost diameter of $10$ cm and outermost diameter of $20$ cm. The maximum storage density of the disk is $1400$ bits/cm. The disk ro...

Ishrat Jahan

22.3k views

Ishrat Jahan asked Nov 2, 2014

24 votes

3 answers

5

GATE CSE 2021 Set 2 | Question: 20
Consider a computer system with $\text{DMA}$ support. The $\text{DMA}$ module is transferring one $8$-bit character in one $\text{CPU}$ cycle from a device to memory through cycle stealing at regular intervals. Consider a $\text{2 MHz}$ ... $\text{DMA}$, the data transfer rate of the device is __________ bits per second.

Consider a computer system with $\text{DMA}$ support. The $\text{DMA}$ module is transferring one $8$-bit character in one $\text{CPU}$ cycle from a device to memory thro...

Arjun

11.4k views

Arjun asked Feb 18, 2021

1 votes

1 answer

6

COA - DMA
A hard disk with a transfer rate of 1 Mbytes/ second is constantly transferring data to memory using DMA. The processor runs at 500 MHz, and takes 500 and 1000 clock cycles to initiate and complete DMA transfer respectively. If the size of the transfer is 1 Kbytes, what is the percentage of processor time consumed for the transfer operation?________(Rounded off to three decimal)

A hard disk with a transfer rate of 1 Mbytes/ second is constantly transferring data to memory using DMA. The processor runs at 500 MHz, and takes 500 and 1000 clock cycl...

ajayraho

598 views

ajayraho asked Nov 21, 2023

9 votes

3 answers

7

GATE CSE 2022 | Question: 7
Which one of the following facilitates transfer of bulk data from hard disk to main memory with the highest throughput? $\text{DMA}$ based $\text{I/O}$ transfer Interrupt driven $\text{I/O}$ transfer Polling based $\text{I/O}$ transfer Programmed $\text{I/O}$ transfer

Which one of the following facilitates transfer of bulk data from hard disk to main memory with the highest throughput?$\text{DMA}$ based $\text{I/O}$ transferInterrupt d...

Arjun

5.1k views

Arjun asked Feb 15, 2022

0 votes

1 answer

8

Gate
An I/O device transfers data at a rate of 10MB/s over a 100MB/S bus. The data is transferred in 4KB blocks. If the processor operates at 500MHz, and it takes a total of 5000 cycles to handle each DMA request, find the fraction of CPU time handling the data transfer with and without DMA.

An I/O device transfers data at a rate of 10MB/s over a 100MB/S bus. The data is transferred in 4KB blocks. If the processor operates at 500MHz, and it takes a total of 5...

Praful jha

677 views

Praful jha asked Jul 7, 2023

3 votes

2 answers

9

I/O Modes | Process State Transition | COA & OS
MSQ A ‘Running’ process is surely put into ‘Blocked/Wait’ state during while requesting for an I/O, in which of the following I/O modes? Synchronous I/O Asynchronous I/O Interrupt Driven I/O DMA

MSQA ‘Running’ process is surely put into ‘Blocked/Wait’ state during while requesting for an I/O, in which of the following I/O modes?Synchronous I/OAsynchronous...

Souvik33

786 views

Souvik33 asked Dec 2, 2022

0 votes

1 answer

10

DMA
The below question is from Made Easy Test series The diagram shows single bus detached DMA configuration for a system. How many times system bus is used for single data transfer using DMA(Consider only data transfer, not command or status transfer) 1 2 3 0 Here answer ... My Doubt: In DMA their is direct data transfer from i/o to memory so system bus is accessed only once. Is this correct?

The below question is from Made Easy Test seriesThe diagram shows single bus detached DMA configuration for a system. How many times system bus is used for single data tr...

Chaitanya Kale

1.4k views

Chaitanya Kale asked Sep 24, 2022

1 votes

2 answers

11

University Assignment
Question → Consider a system in which bus cycles take 500 ns. Transfer of bus control in either direction, from processor to I/O device or vice-versa, takes 250 ns. One of the I/O devices has a data transfer rate of 50 KB/s and employs DMA. ... For how long would the device tie up the bus when transferring a block of 128 bytes? b)Repeat the calculation for cycle-stealing mode

Question → Consider a system in which bus cycles take 500 ns. Transfer of bus control in either direction, from processor to I/O device or vice-versa, takes 250 ns. One...

lalitver10

725 views

lalitver10 asked Sep 18, 2022

1 votes

1 answer

12

GATE Overflow Test Series | Mock GATE | Test 6 | Question: 39
A Hard disk is connected to a $2$ GHz processor through a DMA controller. Assume that the initial setup time for a DMA transfer takes $800$ clock cycles for the processor and also assume that the handling of the ... time consumed by the disk, assuming that the data are transferred only during the idle cycles of the CPU is _______

A Hard disk is connected to a $2$ GHz processor through a DMA controller. Assume that the initial setup time for a DMA transfer takes $800$ clock cycles for the processor...

Arjun

287 views

Arjun asked Jan 30, 2022

0 votes

1 answer

13

DMA cycle stealing
Consider a device with 1MB per second transfer rate and operating in cycle stealing mode of DMA. It requires 0.5 microsecond to transfer the data (1 byte) when it is ready or prepared. Percentage of CPU blocked due to DMA?

Consider a device with 1MB per second transfer rate and operating in cycle stealing mode of DMA. It requires 0.5 microsecond to transfer the data (1 byte) when it is read...

Ajit J

1.3k views

Ajit J asked Dec 9, 2018

0 votes

1 answer

14

DMA Transfer rate
Consider 8-bit DMA device operating in cycle stealing mode (Single Transfer Mode). Each DMA cycle takes 6 clock and each clock is of 2 MHz. An intermediate CPU machine cycle take 2 μsec. What is the data transfer rate of DMA? Ans. 200 KB/sec

Consider 8-bit DMA device operating in cycle stealing mode (Single Transfer Mode). Each DMA cycle takes 6 clock and each clock is of 2 MHz. An intermediate CPU machine cy...

Na462

1.1k views

Na462 asked Jul 23, 2018

4 votes

2 answers

15

Andrew S. Tanenbaum (OS) Edition 4 Exercise 5 Question 5 (Page No. 429)
A DMA controller has five channels. The controller is capable of requesting a $32$-bit word every $40\: nsec.$ A response takes equally long. How fast does the bus have to be to avoid being a bottleneck?

A DMA controller has five channels. The controller is capable of requesting a $32$-bit word every $40\: nsec.$ A response takes equally long. How fast does the bus have t...

admin

2.2k views

admin asked Oct 28, 2019

1 votes

1 answer

16

Andrew S. Tanenbaum (OS) Edition 4 Exercise 5 Question 7 (Page No. 430)
One mode that some DMA controllers use is to have the device controller send the word to the DMA controller, which then issues a second bus request to write to memory. How can this mode be used to perform ... Discuss any advantage or disadvantage of using this method instead of using the CPU to perform memory to memory copy.

One mode that some DMA controllers use is to have the device controller send the word to the DMA controller, which then issues a second bus request to write to memory. Ho...

admin

640 views

admin asked Oct 28, 2019

5 votes

1 answer

17

GATE Overflow Test Series | Mock GATE | Test 3 | Question: 50
A device with transfer rate of $25$ KBps is connected to a CPU. Data is transferred byte-wise. Let the interrupt overhead be $12$ microseconds. The byte transfer time between the device interface register and CPU or memory is negligible. What is the minimum performance gain of operating device under interrupt driven mode?

A device with transfer rate of $25$ KBps is connected to a CPU. Data is transferred byte-wise. Let the interrupt overhead be $12$ microseconds. The byte transfer time bet...

gatecse

592 views

gatecse asked Jan 26, 2021

4 votes

1 answer

18

GATE Overflow Test Series | Mock GATE | Test 3 | Question: 55
Consider a DMA controller transferring $32$ bit words to memory using cycle stealing. The words are assembled from a device that transmits bytes at a rate of $24$ Mbytes per second. The CPU fetches and executes instructions at an average rate of $2$ billion ... down because of the DMA transfer? $0.6 \%$ $0.12 \%$ $0.3 \%$ $0.10 \%$

Consider a DMA controller transferring $32$ bit words to memory using cycle stealing. The words are assembled from a device that transmits bytes at a rate of $24$ Mbytes ...

gatecse

569 views

gatecse asked Jan 26, 2021

1 votes

1 answer

19

DMA - Data Transfer Rate
A computer consists of a CPU and an I/O device D connected to main memory M via a shared bus with a data bus width of one word (16-bits). The CPU can execute a maximum of 106 instructions per second. An average instruction requires six processor cycles, three of which use the memory ... or status-checking time] ? (A) 2.15 x 106 (B) 3.15 x 106 (C) 1.15 x 106 (D) 4.15 x 106

A computer consists of a CPU and an I/O device D connected to main memory M via a shared bus with a data bus width of one word (16-bits). The CPU can execute a maximum of...

ankitgupta.1729

1.4k views

ankitgupta.1729 asked Dec 20, 2017

9 votes

5 answers

20

ISRO-2013-14
A processor is fetching instructions at the rate of $1$ MIPS. A DMA module is used to transfer characters to RAM from a device transmitting at $9600$ bps. How much time will the processor be slowed down due to DMA activity? $9.6$ms $4.8$ms $2.4$ms $1.2$ms

A processor is fetching instructions at the rate of $1$ MIPS. A DMA module is used to transfer characters to RAM from a device transmitting at $9600$ bps. How much time w...

makhdoom ghaya

7.2k views

makhdoom ghaya asked Apr 26, 2016

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