Search results for gate2016-1+digital-logic

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Digital electronics ECE set-3 Gate 2016`
For the circuit shown in the figure, the delay of the bubbled NAND gate is 2ns and that of the counter is assumed to be zero If the clock (Clk) frequency is 1GHz, then the counter behaves as a (A) mod-5 counter (B) mod-6 counter (C) mod-7 counter (D) mod-8 counter

For the circuit shown in the figure, the delay of the bubbled NAND gate is 2ns and that of the counter is assumed to be zeroIf the clock (Clk) frequency is 1GHz, then the...

rahul sharma 5

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rahul sharma 5 asked Sep 10, 2017

1 votes

0 answers

Digital Logic ECE 2016 Set 1

rahul sharma 5

540 views

rahul sharma 5 asked Dec 23, 2016

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