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Search results for hazards
7
votes
1
answer
1
GO Classes Test Series 2024 | Mock GATE | Test 12 | Question: 49
Consider the following code fragment: Identify all data dependencies (potential data hazards) in the given code snippet within one loop iteration. Let the number of true data dependencies be $\mathrm{X}$ ... output dependencies be $\text{Z}$. What is $\mathrm{X}+2 \mathrm{Y}+3 \mathrm{Z}?$
Consider the following code fragment:Identify all data dependencies (potential data hazards) in the given code snippet within one loop iteration. Let the number of true d...
GO Classes
1.0k
views
GO Classes
asked
Jan 21
CO and Architecture
goclasses2024-mockgate-12
goclasses
numerical-answers
co-and-architecture
data-hazards
data-dependency
2-marks
+
–
2
votes
3
answers
2
Calculate sum of (WAR, RAW and WAW) dependencies instructions.
Consider the following instructions. I 1 : R 1 = 100 I 2 : R 1 = R 2 + R 4 I 3 : R 2 = R 4 + 25 I 4 : R 4 = R 1 + R 3 I 5 : R 1 = R 1 + 30 Calculate sum of (WAR, RAW and WAW) dependencies the above instructions. (a) 10 (c) 6 (b) 12 (d) 8
Consider the following instructions.I 1 : R 1 = 100I 2 : R 1 = R 2 + R 4I 3 : R 2 = R 4 + 25I 4 : R 4 = R�...
sunil sarode
5.4k
views
sunil sarode
asked
Sep 28, 2017
CO and Architecture
data-dependency
data-hazards
+
–
1
votes
1
answer
3
Applied Test Series
Consider the following sequence of instructions: LOAD R4, 0(R8) AND R1, R5, R2 OR R1, R1, R3 OR R2, R2, R7 ADD R3, R2, R1 STORE R3, 0(R8) Number of cycles required to complete the given sequence of instructions in a 5 stage (IF, ID, EX, Mem, WB) RISC processor with operand forwarding_____
Consider the following sequence of instructions: LOAD R4, 0(R8) AND R1, R5, R2 OR R1, R1, R3 OR R2, R2, R7 ADD R3, R2, R1 STORE R3, 0(R8) Number of cycles required to com...
LRU
567
views
LRU
asked
Jan 8, 2022
CO and Architecture
test-series
co-and-architecture
pipelining
data-hazards
+
–
0
votes
1
answer
4
Applied Gate Test Series
How to solve this?
How to solve this?
imkeshav
748
views
imkeshav
asked
Jan 6, 2022
CO and Architecture
test-series
co-and-architecture
data-hazards
+
–
1
votes
1
answer
5
Applied Test Series
Consider following assembly-language program: 1: MOV R3, R7 2: LOAD R8, (R3) 3: ADD R3, R3, 4 4: LOAD R9, (R3) 5: BNE R8, R9, L3 The sum of WAW, RAW, and WAR dependencies from the given code are_________
Consider following assembly-language program:1: MOV R3, R7 2: LOAD R8, (R3) 3: ADD R3, R3, 4 4: LOAD R9, (R3) 5: BNE R8, R9, L3The sum of WAW, RAW, and WAR dependencies f...
LRU
513
views
LRU
asked
Jan 8, 2022
CO and Architecture
test-series
co-and-architecture
data-hazards
+
–
1
votes
0
answers
6
applied gate mock 10
why option 3 is right AND FOLLOW RAW HOW?
why option 3 is right AND FOLLOW RAW HOW?
jugnu1337
211
views
jugnu1337
asked
Dec 14, 2021
CO and Architecture
co-and-architecture
data-hazards
+
–
1
votes
4
answers
7
Madeeasy- Types of Dependencies
Please clarify along with the names.
Please clarify along with the names.
Markzuck
1.4k
views
Markzuck
asked
Jan 9, 2019
CO and Architecture
co-and-architecture
data-dependency
data-hazards
pipelining
databases
+
–
0
votes
1
answer
8
Avoiding pipeline Hazards
Please Confirm.
Please Confirm.
smsubham
461
views
smsubham
asked
Dec 27, 2018
CO and Architecture
pipelining
hazards
co-and-architecture
data-hazards
data-dependency
+
–
11
votes
4
answers
9
ISRO2016-11
The dynamic hazard problem occurs in combinational circuit alone sequential circuit only Both (a) and (b) None of the above
The dynamic hazard problem occurs incombinational circuit alonesequential circuit onlyBoth (a) and (b)None of the above
Desert_Warrior
11.7k
views
Desert_Warrior
asked
Jul 3, 2016
Digital Logic
isro2016
digital-logic
digital-circuits
hazards
+
–
1
votes
1
answer
10
Various Methods to eliminate Static(0/1) and Dynamic Hazards in Digital Circuits
Hi Guys, What are various techniques to eliminate Static(0/1) and Dynamic Hazards in Digital Circuits ? If you can provide some good reference then it will be really helpful. ping @Puja Mishra, ... , @Anu007, @Hemant Parihar, @ sushmita, @VS @Shweta Nair @Krish__, @Ashwin Kulkarni @reena_kandari and @srestha ji.
Hi Guys,What are various techniques to eliminate Static(0/1) and Dynamic Hazards in Digital Circuits ?If you can provide some good reference then it will be really helpfu...
Chhotu
424
views
Chhotu
asked
Dec 29, 2017
Digital Logic
digital-circuits
hazards
+
–
1
votes
1
answer
11
RAW, WAR, WAW hazards
J1: R1 = 100 J2: R1 = R2 + R4 J3: R2 = R4 + 25 J4: R4 = R1 + R3 J5: R1 = R1 + 30 Give the no of RAW, WAR and WAW hazards
J1: R1 = 100J2: R1 = R2 + R4J3: R2 = R4 + 25J4: R4 = R1 + R3J5: R1 = R1 + 30Give the no of RAW, WAR and WAW hazards
Tuhin Dutta
2.1k
views
Tuhin Dutta
asked
Dec 3, 2017
CO and Architecture
data-hazards
data-dependency
co-and-architecture
hazards
+
–
3
votes
2
answers
12
Pipeline hazards
R1 <- R1+R2 R2 <- R3*R4 R3 <- R4-R1 R2 <- R3+R4 Can someone point out hazards. Thanks :)
R1 <- R1+R2R2 <- R3*R4R3 <- R4-R1R2 <- R3+R4Can someone point out hazards. Thanks :)
gauravkc
1.2k
views
gauravkc
asked
Jan 24, 2018
CO and Architecture
pipelining
hazards
co-and-architecture
data-hazards
+
–
2
votes
3
answers
13
RAW hazard
Find total number of RAW hazards. Doubt: Should I4 - I5 be counted or not ?
Find total number of RAW hazards.Doubt: Should I4 - I5 be counted or not ?
just_bhavana
1.7k
views
just_bhavana
asked
Aug 27, 2017
CO and Architecture
co-and-architecture
hazards
+
–
4
votes
1
answer
14
Dependency VS Hazard
Consider following program is executed on a 5 stage RISC pipeline and stages are IF, ID, EX, MA, WB. IF = Instruction Fetch ID = Instruction Decode and fetch register EX = Execution Stage MA = Memory Access WB = Write back register file Program: ... and Hazards.(There is no Structural Dependency) My Answers -> Dependencies = 6, hazards = 3. Someone verify these answer.
Consider following program is executed on a 5 stage RISC pipeline and stages are IF, ID, EX, MA, WB.IF = Instruction FetchID = Instruction Decode and fetch register EX =...
Shubhanshu
2.4k
views
Shubhanshu
asked
Nov 8, 2017
CO and Architecture
co-and-architecture
pipelining
hazards
+
–
1
votes
0
answers
15
Morris Mano Edition 3 Exercise 9 Question 22 (Page No. 396)
Find a circuit that has no static hazard and implements the boolean function: F(A,B,C,D) = $\sum(0,2,6,7,8,10,12)$
Find a circuit that has no static hazard and implements the boolean function:F(A,B,C,D) = $\sum(0,2,6,7,8,10,12)$
ajaysoni1924
1.3k
views
ajaysoni1924
asked
Apr 8, 2019
Digital Logic
digital-logic
morris-mano
sequential-circuit
synchronous-asynchronous-circuits
hazards
+
–
0
votes
2
answers
16
Sum of Data dependencies
$I_1 : MUL \ \ \ \ \ R_1, R_2, R_3$ // $R_1 \leftarrow R_2 \times R_3$ $I_2 : ADD \ \ \ \ \ R_4, R_4, R_1$ $I_3 : MUL \ \ \ \ \ R_1, R_5, R_6$ $I_4 : SUB \ \ \ \ \ R_4, R_4, R_1$ Sum of RAW, WAR and WAW dependencies is _____.
$I_1 : MUL \ \ \ \ \ R_1, R_2, R_3$ // $R_1 \leftarrow R_2 \times R_3$$I_2 : ADD \ \ \ \ \ R_4, R_4, R_1$$I_3 : MUL \ \ \ \ \ R_1, R_5, R_6$$I_4 : SUB...
Mk Utkarsh
785
views
Mk Utkarsh
asked
Oct 23, 2018
CO and Architecture
data-hazards
data-dependency
co-and-architecture
numerical-answers
+
–
1
votes
0
answers
17
Morris Mano Edition 3 Exercise 9 Question 23 (Page No. 396)
Draw the logic diagram of the product of sum expression $ Y = (x _1 + x _2’)(x _2 + x _3)$ Show that there is a static 0 hazard when $x _1$ and $x _3$ is equal to zero and $x _2$ goes from 0 to 1.Find a way to remove hazard by adding one more OR gate.
Draw the logic diagram of the product of sum expression$ Y = (x _1 + x _2’)(x _2 + x _3)$Show that there is a static 0 hazard when $x _1$ and $x _3$ is equal to zero a...
ajaysoni1924
731
views
ajaysoni1924
asked
Apr 8, 2019
Digital Logic
digital-logic
morris-mano
sequential-circuit
synchronous-asynchronous-circuits
hazards
+
–
0
votes
0
answers
18
SELF DOUBT
PLEASE ANYONE REFER ANY VIDEO OF DATA HAZARDS OR SOME NOTES SOME LINK ...NOT GETTING ENOUGH EXPLANATION OF DATA HAZARD HERE . IF SOMEONE KNOWS THE CONCEPT THEN Consider the following Instruction sequence I1: ADD R1,R2,R1 I2: LW R2,0(R1) I3: LW ... 4 (D) 1 then plss explain this question solution step by step otherwise give the link ? and cases like with pipelining without pipelining
PLEASE ANYONE REFER ANY VIDEO OF DATA HAZARDS OR SOME NOTES SOME LINK……………...NOT GETTING ENOUGH EXPLANATION OF DATA HAZARD HERE .IF SOMEONE KNOWS THE CONCEPT T...
Deepanshu
2.1k
views
Deepanshu
asked
Dec 31, 2018
CO and Architecture
co-and-architecture
data-hazards
+
–
2
votes
1
answer
19
Pipeline : Number of RAW dependencies
Consider the below instructions executed on a 5 stage(IF,ID,EX,MA,WB) RISC pipeline with operand forwarding. I1: ADD R0,R1,R2 (R0=R1+R2) I2: SUB R3,R0,R2 I3:MUL R4,R3,R0 I4:DIV R5,R4,R0 How many RAW dependencies?
Consider the below instructions executed on a 5 stage(IF,ID,EX,MA,WB) RISC pipeline with operand forwarding.I1: ADD R0,R1,R2 (R0=R1+R2)I2: SUB R3,R0,R2I3:MUL R4,R3,R0I4:D...
Mk Utkarsh
2.3k
views
Mk Utkarsh
asked
Oct 23, 2018
CO and Architecture
data-hazards
hazards
co-and-architecture
pipelining
data-dependency
+
–
0
votes
1
answer
20
UPPCL AE 2018:13
Which of the following statements is true? Write after Read $\text{(WAR)}$ hazard can be mitigated by data forwarding. Both $\text{WAW}$ and $\text{WAR}$ hazards can be mitigated by data forwarding. None of the above Write after Write $\text{(WAW)}$ hazard can be mitigated by data forwarding.
Which of the following statements is true?Write after Read $\text{(WAR)}$ hazard can be mitigated by data forwarding.Both $\text{WAW}$ and $\text{WAR}$ hazards can be mit...
admin
443
views
admin
asked
Jan 5, 2019
CO and Architecture
uppcl2018
co-and-architecture
data-hazards
+
–
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