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Search results for ies
2
votes
2
answers
1
IES 2018_Digital Logic_Counter
For what minimum value of propagation delay in each filp-flop will a 10 bit ripple counter skip a count, when it is clocked at 10 MHz? a) 5 ns b) 10 ns c) 20 ns d) 40 ns
For what minimum value of propagation delay in each filp-flop will a 10 bit ripple counter skip a count, when it is clocked at 10 MHz?a) 5 nsb) 10 nsc) 20 nsd) 40 ns
sh!va
2.6k
views
sh!va
asked
Jan 9, 2018
Digital Logic
digital-logic
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ies-2018
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1
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2
IES 2018 - Round robin, FCFS, SJF comparison
Consider the following set of processes First Come First Serve (FCFS), non preemptive Shortest Job First (SJF) and Round Robin (RR) (quantum = 10 ms). Scheduling Algorithms for this process set would imply which of the following features? 1. The SJF policy results in less than ... below. (a) 1, 2 and 3 (b) 1 and 2 only (c) 1 and 3 only (d) 2 and 3 only
Consider the following set of processesFirst Come First Serve (FCFS), non preemptive Shortest Job First (SJF) and Round Robin (RR) (quantum = 10 ms). Scheduling Algorithm...
sh!va
715
views
sh!va
asked
Jan 9, 2018
Operating System
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1
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3
IES 2018 JK Flip flop
In a master slave JK flip-flop (a) both master and slave are positive edge triggered (b) both master and slave are negative edge triggered (c) master is positive edge triggered and slave is negative edge triggered (d) master is negative edge triggered and slave is positive edge triggered
In a master slave JK flip-flop(a) both master and slave are positive edge triggered(b) both master and slave are negative edge triggered(c) master is positive edge trigge...
sh!va
420
views
sh!va
asked
Jan 9, 2018
Digital Logic
digital-logic
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ies-2018
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2
votes
1
answer
4
IEs 2018- Computer Networks
Which of the following statements is correct in respect of TCP and UDP protocols? (a) TCP is connection-oriented, whereas UDP is connectionless (b) TCP is connectionless, whereas UDP is connection-oriented (c) Both are connectionless (d) Both are connection-oriented
Which of the following statements is correct in respect of TCP and UDP protocols?(a) TCP is connection-oriented, whereas UDP is connectionless(b) TCP is connectionless, w...
sh!va
2.4k
views
sh!va
asked
Jan 9, 2018
Computer Networks
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1
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5
IES 2018- Computer Networks
The technique for using one set of addresses inside a network and remapping those addresses to a different set of addresses that are seen outside the local network on the internet is called (a) network address translation (b) address resolution (c) network address mapping (d) virtual LAN
The technique for using one set of addresses inside a network and remapping those addresses to a different set of addresses that are seen outside the local network on the...
sh!va
553
views
sh!va
asked
Jan 9, 2018
Computer Networks
ies-2018
ies
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1
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6
IES 2018- Computer networks
What type of network is the Internet? (a) Circuit-switched network (b) Message-switched network (c) Packet-switched network (d) Cell-switched network
What type of network is the Internet?(a) Circuit-switched network(b) Message-switched network(c) Packet-switched network(d) Cell-switched network
sh!va
352
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sh!va
asked
Jan 9, 2018
Computer Networks
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1
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7
IES 2018 - Round robin scheduling
Three processors with their respective process IDs given by P1, P2 and P3, having estimated completion time of 8 ms, 4 ms and 2 ms, respectively, enter a ready queue together in the order P1, P2 and P3. What is the average turn time in the Round Robin Scheduling Algorithm with time 2 ms? (a) 10 ms (b) 15 ms (c) 20 ms (d) 25 ms
Three processors with their respective process IDs given by P1, P2 and P3, having estimated completion time of 8 ms, 4 ms and 2 ms, respectively, enter a ready queue toge...
sh!va
1.0k
views
sh!va
asked
Jan 9, 2018
Operating System
round-robin-scheduling
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ies-2018
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1
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1
answer
8
IES 2018 Program Structure
A program structure that permits repeated operation of a particular sequence of instructions is known as (a) subroutine (b) loop (c) module (d) microprogramming
A program structure that permits repeated operation of a particular sequence of instructions is known as(a) subroutine(b) loop(c) module(d) microprogramming
sh!va
432
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sh!va
asked
Jan 9, 2018
Programming in C
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programming
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0
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9
IES 2018- Interrupts
Statement I : The internal interrupt is initiated by some exceptional condition caused by the program itself rather than by an external event. Statement II :External interrupt depends on external conditons that are independent of the program being executed at the time. (a) ... I (c) Statements I is true but statement II is false (d) Statement I is false but statement II is true
Statement I : The internal interrupt is initiated by some exceptional condition caused by the program itself rather than by an external event.Statement II :External inter...
sh!va
395
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sh!va
asked
Jan 9, 2018
CO and Architecture
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co-and-architecture
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10
IES 2018_Digital Logic
In large radar installations, it is required to translate the angular position of a shaft into digital information. this is most generally achieved by employing a code wheel. For unambiguous sensing of the shaft position, one employs a/an a) Octal Code b) BCD code c) Binary Gray code d) Natural binary code
In large radar installations, it is required to translate the angular position of a shaft into digital information. this is most generally achieved by employing a code wh...
sh!va
393
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sh!va
asked
Jan 9, 2018
Digital Logic
ies-2018
ies
digital-logic
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0
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11
IES 2018_Digital Logic_ripple counter
In a 4-stage ripple counter, the propagation delay of a flip flop is 30 ns. If the pulse width of the strobe is 30 ns, the maximum frequency at which the counter operates reliably is nearly_________ (a) 9.7 MHz (b) 8.4 MHz (c) 6.7 MHz (d) 4.4 MHz
In a 4-stage ripple counter, the propagation delay of a flip flop is 30 ns. If the pulse width of the strobe is 30 ns, the maximum frequency at which the counter operates...
sh!va
348
views
sh!va
asked
Jan 9, 2018
Digital Logic
digital-logic
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ies-2018
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1
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1
answer
12
IES 2018 Memory hit miss ratio
Consider that a level of the memory hierarchy has a hit rate of 80%. Memory requests take 10 ns to complete if they hit in the level, and memory requests that miss in the level take 100 ns to complete. The average access time of the level is (a) 110 ns (b) 100 ns (c) 80 ns (d) 28 ns
Consider that a level of the memory hierarchy has a hit rate of 80%. Memory requests take 10 ns to complete if they hit in the level, and memory requests that miss in the...
sh!va
375
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sh!va
asked
Jan 9, 2018
CO and Architecture
co-and-architecture
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13
IES 2018 - DOS Windows Unix comparison
Statement I : MS DOS and Windows products have always used implicit mounting when an attempt is first made to access the media. Statement II : Unix has traditionally used explicit mount command to access the removable medium. (a) Both statemnts I and ... I (c) Statements I is true but statement II is false (d) Statement I is false but statement II is true
Statement I : MS DOS and Windows products have always used implicit mounting when an attempt is first made to access the media.Statement II : Unix has traditionally used...
sh!va
322
views
sh!va
asked
Jan 9, 2018
Operating System
ies-2018
ies
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1
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14
IES 2018 -Static memory
Statement I : Static RAM memory devices retain data for as long as power is supplied. Statement II : SRAM is used when the size of read/write memory required is large. (a) Both statemnts I and statement II are individually true and statement II is the ... of statement I (c) Statements I is true but statement II is false (d) Statement I is false but statement II is true
Statement I : Static RAM memory devices retain data for as long as power is supplied.Statement II : SRAM is used when the size of read/write memory required is large.(a) ...
sh!va
306
views
sh!va
asked
Jan 9, 2018
CO and Architecture
ies
ies-2018
co-and-architecture
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1
votes
0
answers
15
IES 2018_Digital Logic
An ADC has a total conversion time of 200 μs. What is the highest frequency that its analog input should be allowed to contain? a ) 2.5 KHz b ) 25 KHz c) 250 KHz d) 0.25 KHz
An ADC has a total conversion time of 200 μs. What is the highest frequency that its analog input should be allowed to contain?a ) 2.5 KHzb ) 25 KHzc) 250 KHzd) 0.25 KHz...
sh!va
366
views
sh!va
asked
Jan 9, 2018
Digital Logic
digital-logic
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ies-2018
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0
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16
IES 2018- Virtual memory
Statement I : Virtual memory is designated virtual because there is no such memory inside the computer. Statement II : Virtual memory uses some space of the hard disk as an extension of the primary storage of the computer. (a) Both statements I and statement ... statement I (c) Statements I is true but statement II is false (d) Statement I is false but statement II is true
Statement I : Virtual memory is designated virtual because there is no such memory inside the computer.Statement II : Virtual memory uses some space of the hard disk as a...
sh!va
310
views
sh!va
asked
Jan 9, 2018
Operating System
ies-2018
ies
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0
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17
IES 2018- Stack memory
Statement I : Stack is organized as 8-bit storage in the microprocessor. Statement II : Stack is a set of memory locations in R/W memory reserved for storing information temporarily during the execution of a program. (a) Both statemnts I and statement II are ... statement I (c) Statements I is true but statement II is false (d) Statement I is false but statement II is true
Statement I : Stack is organized as 8-bit storage in the microprocessor.Statement II : Stack is a set of memory locations in R/W memory reserved for storing information t...
sh!va
350
views
sh!va
asked
Jan 9, 2018
CO and Architecture
ies
ies-2018
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1
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0
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18
IES 2018 - Memory PLA PROM
Statement I : PLA contains a fixed AND array and a programmable OR array. Statement II : PROM contains a fixed AND array and a programmable OR array. (a) Both statemnts I and statement II are individually true and statement II is the correct explanation of ... statement I (c) Statements I is true but statement II is false (d) Statement I is false but statement II is true
Statement I : PLA contains a fixed AND array and a programmable OR array.Statement II : PROM contains a fixed AND array and a programmable OR array.(a) Both statemnts I a...
sh!va
257
views
sh!va
asked
Jan 9, 2018
Digital Logic
ies
ies-2018
digital-logic
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1
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0
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19
IES 2018- 8085 programming
In the following 8085 assembly language program, assume that the carry flag is initially reset. What is the content of the accumulator after the execution of the program? MVI A, 04H RRC MOV B, A RLC RLC ADD B RCC (a) 02H (b) 05H (c) 15H (d) 25H
In the following 8085 assembly language program, assume that the carry flag is initially reset. What is the content of the accumulator after the execution of the program?...
sh!va
283
views
sh!va
asked
Jan 9, 2018
CO and Architecture
ies
ies-2018
digital-logic
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1
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0
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20
IES 2018_Digital logic (Mealy Model)
Consider the following opinions regarding the advantage and disadvantage of a Mealy model: 1. Advantage: Less number of states (hence less hardware) Disadvantage: Input transients are directly conveyed to output 2. Advantage: Output remains stable over entire clock period Disadvantage: ... the above is/are correct? (a) 1 only (b) 2 only (c) Both 1 and 2 (d) None
Consider the following opinions regarding the advantage and disadvantage of a Mealymodel:1. Advantage: Less number of states (hence less hardware)Disadvantage: Input tran...
sh!va
236
views
sh!va
asked
Jan 9, 2018
Digital Logic
digital-logic
ies
ies-2018
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