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Search results for instruction-format
66
votes
7
answers
1
GATE CSE 2018 | Question: 51
A processor has $16$ integer registers $\text{(R0, R1}, \ldots ,\text{ R15)}$ and $64$ floating point registers $\text{(F0, F1}, \ldots , \text{F63)}.$ It uses a $2\text{- byte}$ instruction format. There are four categories of ... $\text{(1F)}.$ The maximum value of $\text{N}$ is _________.
A processor has $16$ integer registers $\text{(R0, R1}, \ldots ,\text{ R15)}$ and $64$ floating point registers $\text{(F0, F1}, \ldots , \text{F63)}.$ It uses a $2\text{...
gatecse
24.0k
views
gatecse
asked
Feb 14, 2018
CO and Architecture
gatecse-2018
co-and-architecture
machine-instruction
instruction-format
numerical-answers
2-marks
+
–
24
votes
6
answers
2
GATE CSE 2020 | Question: 44
A processor has $64$ registers and uses $16$-bit instruction format. It has two types of instructions: I-type and R-type. Each I-type instruction contains an opcode, a register name, and a $4$-bit immediate value. Each R-type instruction ... two register names. If there are $8$ distinct I-type opcodes, then the maximum number of distinct R-type opcodes is _______.
A processor has $64$ registers and uses $16$-bit instruction format. It has two types of instructions: I-type and R-type. Each I-type instruction contains an opcode, a re...
Arjun
28.6k
views
Arjun
asked
Feb 12, 2020
CO and Architecture
gatecse-2020
co-and-architecture
numerical-answers
instruction-format
machine-instruction
2-marks
+
–
49
votes
6
answers
3
GATE CSE 2014 Set 1 | Question: 9
A machine has a $32\text{-bit}$ architecture, with $1\text{-word}$ long instructions. It has $64$ registers, each of which is $32$ bits long. It needs to support $45$ instructions, which have an immediate operand in ... to two register operands. Assuming that the immediate operand is an unsigned integer, the maximum value of the immediate operand is ____________
A machine has a $32\text{-bit}$ architecture, with $1\text{-word}$ long instructions. It has $64$ registers, each of which is $32$ bits long. It needs to support $45$ ins...
go_editor
18.2k
views
go_editor
asked
Sep 26, 2014
CO and Architecture
gatecse-2014-set1
co-and-architecture
machine-instruction
instruction-format
numerical-answers
normal
+
–
67
votes
4
answers
4
GATE CSE 2016 Set 2 | Question: 31
Consider a processor with $64$ registers and an instruction set of size twelve. Each instruction has five distinct fields, namely, opcode, two source register identifiers, one destination register identifier, and twelve-bit immediate value. Each ... program has $100$ instructions, the amount of memory (in bytes) consumed by the program text is _________.
Consider a processor with $64$ registers and an instruction set of size twelve. Each instruction has five distinct fields, namely, opcode, two source register identifiers...
Akash Kanase
20.9k
views
Akash Kanase
asked
Feb 12, 2016
CO and Architecture
gatecse-2016-set2
instruction-format
machine-instruction
co-and-architecture
normal
numerical-answers
+
–
1
votes
2
answers
5
Ace Test Series | COA | Addressing
A system support zero address, one address & two address instructions. Let 16-bit instruction is stored in 128-word memory. Identify the correct among the following. (A) 16K zero address, 128-one address, 2-two address instructions (B) 256 K ... -zero address instructions (C) 28 K zero address, 2-two address, 32-one address instructions (D) None of the above
A system support zero address, one address & two address instructions. Let 16-bit instruction is stored in 128-word memory. Identify the correct among the following.(A) 1...
none30
350
views
none30
asked
Sep 5, 2023
CO and Architecture
co-and-architecture
ace-test-series
instruction-format
+
–
1
votes
0
answers
6
No of 1 Address 2 Address 0 Address Instructions Practice
I have seen lots of questions like this : A load-store architecture in which memory operation applied only on LOAD and STORE instructions and other all operations are REG-REG instructions. Assume three address architecture. Find the minimum number of ... 3AI: 7 2AI:12 1AI:15 0AI:16 Please comment if anything wrong!!!
I have seen lots of questions like this :A load-store architecture in which memory operation applied only on LOAD and STORE instructions and other all operations are REG-...
squirrel69
232
views
squirrel69
asked
Nov 5, 2023
CO and Architecture
machine-instruction
instruction-format
instruction-execution
+
–
1
votes
2
answers
7
GATE@Zeal COA Topic Test
saurabh0709
289
views
saurabh0709
asked
Sep 27, 2023
CO and Architecture
numerical-answers
test-series
co-and-architecture
instruction-format
+
–
2
votes
1
answer
8
Unacademy Computer Organization and Architecture Workbook
consider a system which supports 2-address, 1-address and 0-address instruction. the system has 'i' bits addresses. if there are 'x' 2-addresses instructions and 'y' 1-addresses. then what is maximum number of 0-addresses instructions supported by system
consider a system which supports 2-address, 1-address and 0-address instruction. the system has 'i' bits addresses. if there are 'x' 2-addresses instructions and 'y' 1-ad...
lovish_bhatia
356
views
lovish_bhatia
asked
Aug 13, 2023
CO and Architecture
computer-architecture
instruction-format
+
–
0
votes
1
answer
9
Self Doubt Random Found on Internet
Consider a CPU which supports fixed length instructions. For this CPU a compiler generates 175 instructions for a user program. All the instructions are stored in the memory in byte aligned fashion, occupying a total of 525 bytes space in memory. The minimum possible length of one instruction for the CPU is _______ bits?
Consider a CPU which supports fixed length instructions. For this CPU a compiler generates 175 instructions for a user program. All the instructions are stored in the mem...
deba1014
459
views
deba1014
asked
Aug 10, 2023
CO and Architecture
computer-architecture
co-and-architecture
instruction-format
+
–
0
votes
1
answer
10
Self Doubt Randomly found on Internet
Consider a hypothetical processor which supports 2-address instructions and 1-address instructions both. The system supports 32-bits fixed length instructions. The system has 16KB byte addressable memory. Minimum number of instructions supported by processor is
Consider a hypothetical processor which supports 2-address instructions and 1-address instructions both. The system supports 32-bits fixed length instructions. The system...
deba1014
288
views
deba1014
asked
Aug 11, 2023
CO and Architecture
co-and-architecture
computer-architecture
instruction-format
+
–
0
votes
0
answers
11
Self Doubt Random found on Internet
Consider a system which supports 2-address and 1-address instructions both. System has 20-bits instructions and 7-bits addresses then which of the following is/are the number of 1-address instructions possible for the system?
Consider a system which supports 2-address and 1-address instructions both. System has 20-bits instructions and 7-bits addresses then which of the following is/are the nu...
deba1014
363
views
deba1014
asked
Aug 11, 2023
CO and Architecture
computer-architecture
co-and-architecture
instruction-format
+
–
16
votes
5
answers
12
#ADDRESS INSTRUCTION
Consider the hypothetical processor is supports both 2 address and one address instructions.It has 128 word memory A 16-bit instruction is placed in the one memory word. Q1.What is the range of two address and one address instructions are supported. A)1 to ... 2-address instructions are already existed.How many one address instructions can be supported ? A)128 B)2 C)256 D)32
Consider the hypothetical processor is supports both 2 address and one address instructions.It has 128 word memory A 16-bit instruction is placed in the one memory word.Q...
junaid ahmad
16.6k
views
junaid ahmad
asked
Jul 24, 2017
CO and Architecture
co-and-architecture
cache-memory
machine-instruction
instruction-format
computer-architecture
+
–
0
votes
1
answer
13
instruction-format
Assume an instruction set that uses a fixed 31 bit instruction length. Operand specifies are 4 bits in length. If there are m-three operand instructions in total, then how many two instructions are possible at maximum?
Assume an instruction set that uses a fixed 31 bit instruction length. Operand specifies are 4 bits in length. If there are m-three operand instructions in total, then ho...
someshawasthi
503
views
someshawasthi
asked
Oct 27, 2022
CO and Architecture
co-and-architecture
instruction-format
+
–
0
votes
0
answers
14
Vishvadeep sir DPP, Instructions
Disadvantages of using 2-address instruction in place of 1-address instructions is/are? More memory required for program Larger sized instructions More number of instructions only 1 only 1 & 3 only 2 all 1,2 and 3
Disadvantages of using 2-address instruction in place of 1-address instructions is/are?More memory required for programLarger sized instructionsMore number of instruction...
kanakjyoti
237
views
kanakjyoti
asked
Sep 1, 2022
CO and Architecture
co-and-architecture
instruction-format
+
–
1
votes
1
answer
15
Consider a system which supports only 1-address type instructions. The size of memory the system has is 2^m KB. The system supports ' i ' distinct instructions. The length of an instruction is ____ Bytes?
Consider a system which supports only 1-address type instructions. The size of memory the system has is $2^m$ KB. The system supports ' i ' distinct instructions. The len...
isriram
1.1k
views
isriram
asked
Jun 9, 2022
CO and Architecture
computer-architecture
instruction-format
+
–
42
votes
4
answers
16
GATE CSE 1992 | Question: 01-vi
In an $11$-bit computer instruction format, the size of address field is $4$-bits. The computer uses expanding OP code technique and has $5$ two-address instructions and $32$ one-address instructions. The number of zero-address instructions it can support is ________
In an $11$-bit computer instruction format, the size of address field is $4$-bits. The computer uses expanding OP code technique and has $5$ two-address instructions and ...
Kathleen
13.0k
views
Kathleen
asked
Sep 12, 2014
CO and Architecture
gate1992
co-and-architecture
machine-instruction
instruction-format
normal
numerical-answers
+
–
1
votes
2
answers
17
made easy test series - instruction format
Consider a hypothetical CPU which supports 16-bit instruction, 64 registers and 1 KB memory space. If there exist 12 2-address instructions which use register references and 12 1-address memory reference instructions then how many 0-address instructions are possible?
Consider a hypothetical CPU which supports 16-bit instruction, 64 registers and 1 KB memory space. If there exist 12 2-address instructions which use register references ...
atulcse
601
views
atulcse
asked
Jan 13, 2022
CO and Architecture
co-and-architecture
instruction-format
made-easy-test-series
+
–
1
votes
0
answers
18
GeeksForGeeks AIM 2 - instruction format
Assume that the control memory is 32 bit wide. The micro-instruction format is divided into 3 fields. A micro operation field of 14 bits specifies the micro-operations to be performed. An address selection field specifies a condition based ... . How many bits are in address selection field, address field and the size of control memory in words respectively?
Assume that the control memory is 32 bit wide. The micro-instruction format is divided into 3 fields. A micro operation field of 14 bits specifies the micro-operations to...
atulcse
591
views
atulcse
asked
Jan 15, 2022
CO and Architecture
co-and-architecture
instruction-format
+
–
0
votes
1
answer
19
Computer Organization, Instruction Set Architecture, Gateforum
Consider a system with 16 Registers(Ro,R1,...R8).An instruction SUB Ro,R1 , which is two bytes long,what is the space assigned to the opcode field (in bits) ?
Consider a system with 16 Registers(Ro,R1,...R8).An instruction SUB Ro,R1 , which is two bytes long,what is the space assigned to the opcode field (in bits) ?
Swarnava Bose
889
views
Swarnava Bose
asked
Oct 21, 2021
CO and Architecture
numerical-answers
co-and-architecture
instruction-format
+
–
6
votes
4
answers
20
ISRO2016-24
In which class of Flynn's taxanomy, Von Neumann architecture belongs to? SISD SIMD MIMD MISD
In which class of Flynn's taxanomy, Von Neumann architecture belongs to?SISDSIMDMIMDMISD
sourav.
9.7k
views
sourav.
asked
Jul 3, 2016
CO and Architecture
co-and-architecture
isro2016
instruction-format
+
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