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Search results for isro+isro2015
2
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1
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ISRO2015-EC Computer networks
A communication channel is having a bandwidth of $3000$ Hz. The transmitted power is such that the received Signal-to-Noise ratio is $1023.$ The maximum data rate that can be transmitted error-free through the channel is: $3$ Kbps $3$ Mbps $30$ Kbps $300$ Kbps
A communication channel is having a bandwidth of $3000$ Hz. The transmitted power is such that the received Signal-to-Noise ratio is $1023.$ The maximum data rate that ca...
sh!va
1.5k
views
sh!va
asked
Feb 22, 2017
Computer Networks
isro2015-ece
computer-networks
isro-ece
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–
0
votes
2
answers
2
ISRO 2015-EC Finte State Machine
The following Finite State Machine (FSM) is used to detect a particular pattern in input data stream. Whenever the pattern is matched at input, output is set to '1' or else output is cleared to '0'. For which ... data stream, output goes to '1' twice? (a) 0010011010010101 (b) 0011011010010101 (c) 0101011000010101 (d) 1100100101001010
The following Finite State Machine (FSM) is used to detect a particular pattern in input data stream. Whenever the pattern is matched at input, output is set to '1' or el...
sh!va
1.5k
views
sh!va
asked
Feb 22, 2017
Theory of Computation
isro2015-ece
isro-ece
theory-of-computation
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1
votes
1
answer
3
ISRO2015-EC Pipelining
Pipelining technique is used in microprocessor to improve which of the following parameter? Power dissipation Interrupt latency Die size Maximum clock frequency
Pipelining technique is used in microprocessor to improve which of the following parameter?Power dissipationInterrupt latencyDie sizeMaximum clock frequency
sh!va
928
views
sh!va
asked
Feb 22, 2017
CO and Architecture
isro2015-ece
isro-ece
co-and-architecture
pipelining
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1
votes
1
answer
4
ISRO2015-EC Flipflop
What is the functionality of following digital circuit? A is input data, CLK is system clock ind Y is output. Falling edge detection of input A Clock division by $2$ Rising edge detection of input A Clock division by $4$
What is the functionality of following digital circuit? A is input data, CLK is system clock ind Y is output.Falling edge detection of input AClock division by $2$Rising ...
sh!va
742
views
sh!va
asked
Feb 22, 2017
Digital Logic
isro2015-ece
isro-ece
digital-logic
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