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Search results for isro2011
39
votes
4
answers
1
GATE CSE 2006 | Question: 14, ISRO2011-14
Which one of the following in place sorting algorithms needs the minimum number of swaps? Quick sort Insertion sort Selection sort Heap sort
Which one of the following in place sorting algorithms needs the minimum number of swaps?Quick sortInsertion sortSelection sortHeap sort
Rucha Shelke
25.4k
views
Rucha Shelke
asked
Sep 17, 2014
Algorithms
gatecse-2006
algorithms
sorting
easy
isro2011
+
–
9
votes
3
answers
2
ISRO2011-62
The average depth of a binary search tree is $O(n^{0.5})$ $O(n)$ $O(\log n)$ $O(n \log n)$
The average depth of a binary search tree is$O(n^{0.5})$$O(n)$$O(\log n)$$O(n \log n)$
go_editor
21.5k
views
go_editor
asked
Jun 23, 2016
DS
isro2011
data-structures
binary-search-tree
time-complexity
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–
34
votes
5
answers
3
GATE CSE 2007 | Question: 8, ISRO2011-31
How many $3$-to-$8$ line decoders with an enable input are needed to construct a $6$-to-$64$ line decoder without using any other logic gates? $7$ $8$ $9$ $10$
How many $3$-to-$8$ line decoders with an enable input are needed to construct a $6$-to-$64$ line decoder without using any other logic gates?$7$$8$$9$$10$
Kathleen
21.4k
views
Kathleen
asked
Sep 21, 2014
Digital Logic
gatecse-2007
digital-logic
normal
isro2011
decoder
+
–
6
votes
3
answers
4
ISRO2011-74
In an $RS$ flip-flop, if the $S$ line (Set line) is set high ($1$) and the $R$ line (Reset line) is set low ($0$), then the state of the flip-flop is : Set to $1$ Set to $0$ No change in state Forbidden
In an $RS$ flip-flop, if the $S$ line (Set line) is set high ($1$) and the $R$ line (Reset line) is set low ($0$), then the state of the flip-flop is :Set to $1$Set to $0...
go_editor
3.3k
views
go_editor
asked
Jun 23, 2016
Digital Logic
isro2011
digital-logic
flip-flop
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–
6
votes
4
answers
5
ISRO2011-79
A problem whose language is recursion is called? Unified problem Boolean function Recursive problem Decidable
A problem whose language is recursion is called?Unified problemBoolean functionRecursive problemDecidable
go_editor
4.4k
views
go_editor
asked
Jun 24, 2016
Theory of Computation
isro2011
theory-of-computation
recursive-and-recursively-enumerable-languages
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–
8
votes
4
answers
6
ISRO2011-24
If the page size in a 32-bit machine is 4K bytes then the size of page table is 1 M bytes 2 M bytes 4 M bytes 4 K bytes
If the page size in a 32-bit machine is 4K bytes then the size of page table is1 M bytes2 M bytes4 M bytes4 K bytes
jaiganeshcse94
22.7k
views
jaiganeshcse94
asked
May 27, 2016
Operating System
isro2011
operating-system
paging
virtual-memory
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–
41
votes
6
answers
7
GATE IT 2007 | Question: 6, ISRO2011-25
A processor takes $12$ cycles to complete an instruction I. The corresponding pipelined processor uses $6$ stages with the execution times of $3, 2, 5, 4, 6$ and $2$ cycles respectively. What is the asymptotic speedup assuming that a very large number of instructions are to be executed? $1.83$ $2$ $3$ $6$
A processor takes $12$ cycles to complete an instruction I. The corresponding pipelined processor uses $6$ stages with the execution times of $3, 2, 5, 4, 6$ and $2$ cycl...
Ishrat Jahan
13.4k
views
Ishrat Jahan
asked
Oct 29, 2014
CO and Architecture
gateit-2007
co-and-architecture
pipelining
normal
isro2011
+
–
4
votes
4
answers
8
ISRO2011-26
The in-order traversal of a tree resulted in FBGADCE. Then the pre-order traversal of that tree would result in FGBDECA ABFGCDE BFGCDEA AFGBDEC
The in-order traversal of a tree resulted in FBGADCE. Then the pre-order traversal of that tree would result inFGBDECAABFGCDEBFGCDEAAFGBDEC
Isha Gupta
7.6k
views
Isha Gupta
asked
Jun 15, 2016
DS
isro2011
data-structures
tree-traversal
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–
7
votes
4
answers
9
ISRO2011-16
Consider a direct mapped cache with $64$ blocks and a block size of $16$ bytes. To what block number does the byte address $1206$ map to does not map $6$ $11$ $54$
Consider a direct mapped cache with $64$ blocks and a block size of $16$ bytes. To what block number does the byte address $1206$ map todoes not map$6$$11$$54$
jenny101
9.1k
views
jenny101
asked
Jun 18, 2016
CO and Architecture
isro2011
co-and-architecture
cache-memory
+
–
12
votes
6
answers
10
ISRO2011-10
Below is the precedence graph for a set of tasks to be executed on a parallel processing system $S$. What is the efficiency of this precedence graph on $S$ if each of the tasks $T_1, \dots, T_8$ takes the same time and the system $S$ has five processors? $25\%$ $40\%$ $50\%$ $90\%$
Below is the precedence graph for a set of tasks to be executed on a parallel processing system $S$.What is the efficiency of this precedence graph on $S$ if each of the ...
go_editor
6.9k
views
go_editor
asked
Jun 21, 2016
Operating System
isro2011
operating-system
process-synchronization
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–
5
votes
5
answers
11
ISRO2011-40
Consider the following pseudocode x:=1; i:=1; while ( x <= 500) begin x:=2^x; i:=i+1; end What is the value of $\textsf{i}$ at the end of the pseudocode? $4$ $5$ $6$ $7$
Consider the following pseudocodex:=1; i:=1; while ( x <= 500) begin x:=2^x; i:=i+1; endWhat is the value of $\textsf{i}$ at the end of the pseudocode?$4$$5$$6$$7$
go_editor
5.1k
views
go_editor
asked
Jun 22, 2016
Algorithms
isro2011
algorithms
identify-function
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–
3
votes
3
answers
12
ISRO2011-76
What is the matrix that represents rotation of an object by $\theta^0$ about the origin in $\text{2D}?$ $\cos \theta$ $- \sin \theta$ $\sin \theta$ $\cos \theta$ $\sin \theta$ $- \cos \theta$ $\cos \theta$ $\sin \theta$ $\cos \theta$ $- \sin \theta$ $\cos \theta$ $\sin \theta$ $\sin \theta$ $- \cos \theta$ $\cos \theta$ $\sin \theta$
What is the matrix that represents rotation of an object by $\theta^0$ about the origin in $\text{2D}?$$\cos \theta$$- \sin \theta$$\sin \theta$$\cos \theta$$\sin \theta$...
asu
3.9k
views
asu
asked
Jun 18, 2016
Geometry
isro2011
geometry
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–
11
votes
4
answers
13
ISRO2011-39
Two control signals in microprocessor which are related to Direct Memory Access (DMA) are $\textsf{INTR & INTA}$ $\textsf{RD & WR}$ $\textsf{S0 & S1}$ $\textsf{HOLD & HLDA}$
Two control signals in microprocessor which are related to Direct Memory Access (DMA) are$\textsf{INTR & INTA}$$\textsf{RD & WR}$$\textsf{S0 & S1}$$\textsf{HOLD & HLDA}$
go_editor
6.6k
views
go_editor
asked
Jun 22, 2016
CO and Architecture
isro2011
co-and-architecture
io-handling
dma
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–
4
votes
6
answers
14
ISRO2011-41
If a microcomputer operates at $5$ MHz with an $8$-bit bus and a newer version operates at $20$ MHz with a $32$-bit bus, the maximum speed-up possible approximately will be $2$ $4$ $8$ $16$
If a microcomputer operates at $5$ MHz with an $8$-bit bus and a newer version operates at $20$ MHz with a $32$-bit bus, the maximum speed-up possible approximately will ...
ajit
5.8k
views
ajit
asked
Oct 1, 2015
CO and Architecture
isro2011
co-and-architecture
cpu
+
–
3
votes
2
answers
15
ISRO2011-70
Number of comparisons required for an unsuccessful search of an element in a sequential search organized, fixed length, symbol table of length L is L L/2 (L+1)/2 2L
Number of comparisons required for an unsuccessful search of an element in a sequential search organized, fixed length, symbol table of length L isLL/2(L+1)/22L
ajit
6.9k
views
ajit
asked
Oct 1, 2015
Algorithms
isro2011
algorithms
searching
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–
11
votes
2
answers
16
ISRO2011-5
$\textsf{MOV [BX], AL}$ type of data addressing is called? register immediate register indirect register relative
$\textsf{MOV [BX], AL}$ type of data addressing is called?registerimmediateregister indirectregister relative
amarVashishth
5.7k
views
amarVashishth
asked
Oct 11, 2015
CO and Architecture
isro2011
co-and-architecture
addressing-modes
+
–
10
votes
5
answers
17
ISRO2011-35
How many edges are there in a forest with $v$ vertices and $k$ components? $(v+1) - k$ $(v+1)/2 - k$ $v - k$ $v + k$
How many edges are there in a forest with $v$ vertices and $k$ components?$(v+1) - k$$(v+1)/2 - k$$v - k$$v + k$
ajit
4.2k
views
ajit
asked
Sep 24, 2015
Graph Theory
isro2011
graph-theory
graph-connectivity
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–
4
votes
3
answers
18
ISRO2011-42
The search concept used in associative memory is Parallel search Sequential search Binary search Selection search
The search concept used in associative memory isParallel searchSequential searchBinary searchSelection search
ajit
4.7k
views
ajit
asked
Oct 1, 2015
CO and Architecture
isro2011
co-and-architecture
cache-memory
+
–
4
votes
5
answers
19
ISRO2011-58
In DMA transfer scheme, the transfer scheme other than burst mode is cycle technique stealing technique cycle stealing technique cycle bypass technique
In DMA transfer scheme, the transfer scheme other than burst mode iscycle techniquestealing techniquecycle stealing techniquecycle bypass technique
go_editor
3.5k
views
go_editor
asked
Jun 23, 2016
CO and Architecture
isro2011
co-and-architecture
io-handling
dma
+
–
5
votes
4
answers
20
ISRO2011-46
Which $\textsf{RAID}$ level gives block level striping with double distributed parity? $\textsf{RAID 10}$ $\textsf{RAID 2}$ $\textsf{RAID 6}$ $\textsf{RAID 5}$
Which $\textsf{RAID}$ level gives block level striping with double distributed parity?$\textsf{RAID 10}$$\textsf{RAID 2}$$\textsf{RAID 6}$$\textsf{RAID 5}$
go_editor
3.1k
views
go_editor
asked
Jun 22, 2016
Databases
isro2011
file-system
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