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15 votes
6 answers
2
Simplified Boolean expression for A'BC+AB'C'+A'B'C'+AB'C+ABC
Simplified Boolean expression for A'BC+AB'C'+A'B'C'+AB'C+ABC A . AB B . B'C C . AB+(A'+AB')C D . AB'+BC+B'C'
Simplified Boolean expression for A'BC+AB'C'+A'B'C'+AB'C+ABCA . ABB . B'CC . AB+(A'+AB')CD . AB'+BC+B'C'
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68 votes
4 answers
4
Minimum NAND/NOR Gates - Realization for ExOR,ExNor,Adder,Subtractor
Minimum No of Gates NAND/NOR Ex-OR Ex-Nor Half Adder Half Subtractor Full Adder Full Subtractor NAND ? ? ? ? ? ? NOR ? ? ? ? ? ?
Minimum No of Gates NAND/NOR Ex-OREx-NorHalf AdderHalf SubtractorFull AdderFull SubtractorNAND??????NOR??????
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113 votes
20 answers
5
GATE CSE 2016 Set 1 | Question: 8
We want to design a synchronous counter that counts the sequence $0-1-0-2-0-3$ and then repeats. The minimum number of $\text{J-K}$ flip-flops required to implement this counter is _____________.
We want to design a synchronous counter that counts the sequence $0-1-0-2-0-3$ and then repeats. The minimum number of $\text{J-K}$ flip-flops required to implement this ...
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85 votes
9 answers
7
GATE CSE 2016 Set 1 | Question: 33
Consider a carry look ahead adder for adding two $n$-bit integers, built using gates of fan-in at most two. The time to perform addition using this adder is $\Theta (1)$ $\Theta (\log(n))$ $\Theta (\sqrt{n})$ $\Theta (n)$)
Consider a carry look ahead adder for adding two $n$-bit integers, built using gates of fan-in at most two. The time to perform addition using this adder is$\Theta (1)$$\...
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14 votes
3 answers
9
minimum number of NAND and NOR gates
Is there any systematic approach to find the minimum number of two input NAND gates and two input NOR gates to be used to impelement a binary expression? If there then please elaborate it for the function Y = A'B+B'C+CD' .
Is there any systematic approach to find the minimum number of two input NAND gates and two input NOR gates to be used to impelement a binary expression?If there then ple...
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102 votes
11 answers
12
GATE CSE 2016 Set 2 | Question: 01
Consider the following expressions: $false$ $Q$ $true$ $P\vee Q$ $\neg Q\vee P$ The number of expressions given above that are logically implied by $P \wedge (P \Rightarrow Q)$ is ___________.
Consider the following expressions:$false$$Q$$true$$P\vee Q$$\neg Q\vee P$The number of expressions given above that are logically implied by $P \wedge (P \Rightarrow Q)$...
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47 votes
9 answers
18
GATE CSE 2004 | Question: 18, ISRO2007-31
In an $SR$ latch made by cross-coupling two NAND gates, if both $S$ and $R$ inputs are set to $0$, then it will result in $Q = 0, Q' = 1$ $Q = 1, Q' = 0$ $Q = 1, Q' = 1$ Indeterminate states
In an $SR$ latch made by cross-coupling two NAND gates, if both $S$ and $R$ inputs are set to $0$, then it will result in$Q = 0, Q' = 1$$Q = 1, Q' = 0$$Q = 1, Q' = 1$Inde...
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79 votes
8 answers
19
GATE CSE 2015 Set 2 | Question: 7
The minimum number of $\text{JK}$ flip-flops required to construct a synchronous counter with the count sequence $(0, 0, 1, 1, 2, 2, 3, 3, 0, 0, \ldots)$ is _______.
The minimum number of $\text{JK}$ flip-flops required to construct a synchronous counter with the count sequence $(0, 0, 1, 1, 2, 2, 3, 3, 0, 0, \ldots)$ is _______.
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52 votes
7 answers
20
GATE CSE 2015 Set 1 | Question: 20
Consider a $4$-bit Johnson counter with an initial value of $0000.$ The counting sequence of this counter is $0, 1, 3, 7, 15, 14, 12, 8, 0$ $0, 1, 3, 5, 7, 9, 11, 13, 15, 0$ $0, 2, 4, 6, 8, 10, 12, 14, 0$ $0, 8, 12, 14, 15, 7, 3, 1, 0$
Consider a $4$-bit Johnson counter with an initial value of $0000.$ The counting sequence of this counter is $0, 1, 3, 7, 15, 14, 12, 8, 0$$0, 1, 3, 5, 7, 9, 11, 13, 15, ...
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