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Search results for memory
277
votes
14
answers
1
GATE CSE 2008 | Question: 67
A processor uses $36$ bit physical address and $32$ bit virtual addresses, with a page frame size of $4$ Kbytes. Each page table entry is of size $4$ bytes. A three level page table is used for virtual to physical address translation, where the virtual address is used as ... tables are respectively $\text{20,20,20}$ $\text{24,24,24}$ $\text{24,24,20}$ $\text{25,25,24}$
A processor uses $36$ bit physical address and $32$ bit virtual addresses, with a page frame size of $4$ Kbytes. Each page table entry is of size $4$ bytes. A three level...
Kathleen
76.8k
views
Kathleen
asked
Sep 12, 2014
Operating System
gatecse-2008
operating-system
virtual-memory
normal
+
–
129
votes
19
answers
2
GATE CSE 2004 | Question: 47
Consider a system with a two-level paging scheme in which a regular memory access takes $150$ $nanoseconds$, and servicing a page fault takes $8$ $milliseconds$. An average instruction takes $100$ nanoseconds of CPU time, and two memory accesses. ... execution time? $\text{645 nanoseconds}$ $\text{1050 nanoseconds}$ $\text{1215 nanoseconds}$ $\text{1230 nanoseconds}$
Consider a system with a two-level paging scheme in which a regular memory access takes $150$ $nanoseconds$, and servicing a page fault takes $8$ $milliseconds$. An avera...
gatecse
63.9k
views
gatecse
asked
Sep 5, 2014
CO and Architecture
gatecse-2004
co-and-architecture
virtual-memory
normal
+
–
49
votes
4
answers
3
GATE CSE 2001 | Question: 2.21
Consider a machine with $64$ MB physical memory and a $32$-bit virtual address space. If the page size s $4$ KB, what is the approximate size of the page table? $\text{16 MB}$ $\text{8 MB}$ $\text{2 MB}$ $\text{24 MB}$
Consider a machine with $64$ MB physical memory and a $32$-bit virtual address space. If the page size s $4$ KB, what is the approximate size of the page table?$\text{16 ...
Kathleen
66.7k
views
Kathleen
asked
Sep 14, 2014
Operating System
gatecse-2001
operating-system
virtual-memory
normal
+
–
121
votes
15
answers
4
GATE CSE 2003 | Question: 78
A processor uses $2-level$ page tables for virtual to physical address translation. Page tables for both levels are stored in the main memory. Virtual and physical addresses are both $32$ bits wide. The memory is byte addressable. For virtual to physical address translation, the ... virtual address is approximately (to the nearest $0.5$ ns) $1.5$ ns $2$ ns $3$ ns $4$ ns
A processor uses $2-level$ page tables for virtual to physical address translation. Page tables for both levels are stored in the main memory. Virtual and physical addres...
gatecse
50.1k
views
gatecse
asked
Sep 15, 2014
Operating System
gatecse-2003
operating-system
normal
virtual-memory
+
–
106
votes
7
answers
5
GATE CSE 2013 | Question: 52
A computer uses $46\text{-bit}$ virtual address, $32\text{-bit}$ physical address, and a three-level paged page table organization. The page table base register stores the base address of the first-level table $\text{(T1)}$ ... is $64$ bytes. What is the size of a page in $\textsf{KB}$ in this computer? $2$ $4$ $8$ $16$
A computer uses $46\text{-bit}$ virtual address, $32\text{-bit}$ physical address, and a three–level paged page table organization. The page table base register stores ...
kanikool
37.7k
views
kanikool
asked
Sep 10, 2014
Operating System
gatecse-2013
operating-system
virtual-memory
normal
+
–
51
votes
10
answers
6
GATE CSE 2020 | Question: 53
Consider a paging system that uses $1$-level page table residing in main memory and a $\textsf{TLB}$ for address translation. Each main memory access takes $100$ ns and $\textsf{TLB}$ lookup takes $20$ ns. Each page transfer to/from the disk ... $1$ decimal places) is ___________
Consider a paging system that uses $1$-level page table residing in main memory and a $\textsf{TLB}$ for address translation. Each main memory access takes $100$ ns and $...
Arjun
46.7k
views
Arjun
asked
Feb 12, 2020
Operating System
gatecse-2020
numerical-answers
operating-system
virtual-memory
2-marks
+
–
91
votes
9
answers
7
GATE CSE 2017 Set 1 | Question: 51
Consider a $2$-way set associative cache with $256$ blocks and uses $\text{LRU}$ replacement. Initially the cache is empty. Conflict misses are those misses which occur due to the contention of multiple blocks for the same cache set. Compulsory ... $10$ times. The number of conflict misses experienced by the cache is _________ .
Consider a $2$-way set associative cache with $256$ blocks and uses $\text{LRU}$ replacement. Initially the cache is empty. Conflict misses are those misses which occur d...
Arjun
38.8k
views
Arjun
asked
Feb 14, 2017
CO and Architecture
gatecse-2017-set1
co-and-architecture
cache-memory
conflict-misses
normal
numerical-answers
+
–
78
votes
5
answers
8
GATE CSE 2017 Set 2 | Question: 45
The read access times and the hit ratios for different caches in a memory hierarchy are as given below: ... and $40\%$ are for memory operand fetch. The average read access time in nanoseconds (up to $2$ decimal places) is _________
The read access times and the hit ratios for different caches in a memory hierarchy are as given below:$$\begin{array}{|l|c|c|} \hline \text {Cache} & \text{Read access ...
Madhav
30.1k
views
Madhav
asked
Feb 14, 2017
CO and Architecture
gatecse-2017-set2
co-and-architecture
cache-memory
numerical-answers
+
–
58
votes
4
answers
9
GATE CSE 2013 | Question: 53
A computer uses $46\text{-bit}$ virtual address, $32\text{-bit}$ physical address, and a three-level paged page table organization. The page table base register stores the base address of the first-level table $\text{(T1)},$ which occupies exactly one ... to guarantee that no two synonyms map to different sets in the processor cache of this computer? $2$ $4$ $8$ $16$
A computer uses $46\text{-bit}$ virtual address, $32\text{-bit}$ physical address, and a three–level paged page table organization. The page table base register stores ...
go_editor
30.3k
views
go_editor
asked
Apr 21, 2016
Operating System
gatecse-2013
normal
operating-system
virtual-memory
+
–
80
votes
8
answers
10
GATE CSE 2010 | Question: 48
A computer system has an $L1$ cache, an $L2$ cache, and a main memory unit connected as shown below. The block size in $L1$ cache is $4$ words. The block size in $L2$ cache is $16$ words. The memory access times are $2$ ... $L1$ cache. What is the time taken for this transfer? $2$ nanoseconds $20$ nanoseconds $22$ nanoseconds $88$ nanoseconds
A computer system has an $L1$ cache, an $L2$ cache, and a main memory unit connected as shown below. The block size in $L1$ cache is $4$ words. The block size in $L2$ cac...
go_editor
42.7k
views
go_editor
asked
Sep 30, 2014
CO and Architecture
gatecse-2010
co-and-architecture
cache-memory
normal
barc2017
+
–
53
votes
8
answers
11
GATE IT 2004 | Question: 12, ISRO2016-77
Consider a system with $2$ level cache. Access times of Level $1$ cache, Level $2$ cache and main memory are $1$ $ns$, $10$ $ns$, and $500$ $ns$ respectively. The hit rates of Level $1$ and Level $2$ caches are $0.8$ and $0.9$, respectively. What is the average access time of the system ignoring the search time within the cache? $13.0$ $12.8$ $12.6$ $12.4$
Consider a system with $2$ level cache. Access times of Level $1$ cache, Level $2$ cache and main memory are $1$ $ns$, $10$ $ns$, and $500$ $ns$ respectively. The hit rat...
Ishrat Jahan
29.6k
views
Ishrat Jahan
asked
Nov 1, 2014
CO and Architecture
gateit-2004
co-and-architecture
cache-memory
normal
isro2016
+
–
61
votes
4
answers
12
GATE CSE 2021 Set 2 | Question: 48
Consider a three-level page table to translate a $39-$bit virtual address to a physical address as shown below: The page size is $\text{4 KB} \;(1\text{KB}=2^{10}$ bytes$)$ and page table entry size at every level is $8$ bytes. A ... $P$ across all levels is _________ $\text{KB}$.
Consider a three-level page table to translate a $39-$bit virtual address to a physical address as shown below:The page size is $\text{4 KB} \;(1\text{KB}=2^{10}$ bytes$)...
Arjun
28.8k
views
Arjun
asked
Feb 18, 2021
Operating System
gatecse-2021-set2
numerical-answers
operating-system
memory-management
page-replacement
2-marks
+
–
68
votes
6
answers
13
GATE IT 2006 | Question: 56
For each of the four processes $P_1, P_2, P_3,$ and $P_4$. The total size in kilobytes $(KB)$ ... $\text{S < P < T}$ $\text{S < T < P}$ $\text{T < S < P}$
For each of the four processes $P_1, P_2, P_3,$ and $P_4$. The total size in kilobytes $(KB)$ and the number of segments are given below.$$\small \begin{array}{|c|c|c|}\h...
Ishrat Jahan
29.2k
views
Ishrat Jahan
asked
Nov 1, 2014
Operating System
gateit-2006
operating-system
memory-management
difficult
+
–
127
votes
10
answers
14
GATE CSE 2014 Set 1 | Question: 44
An access sequence of cache block addresses is of length $N$ and contains n unique block addresses. The number of unique block addresses between two consecutive accesses to the same block address is bounded above by $k$. What is the miss ratio if the access sequence is passed ... $\left(\dfrac{1}{N}\right)$ $\left(\dfrac{1}{A}\right)$ $\left(\dfrac{k}{n}\right)$
An access sequence of cache block addresses is of length $N$ and contains n unique block addresses. The number of unique block addresses between two consecutive accesses ...
go_editor
22.8k
views
go_editor
asked
Sep 28, 2014
CO and Architecture
gatecse-2014-set1
co-and-architecture
cache-memory
normal
+
–
83
votes
6
answers
15
GATE CSE 2003 | Question: 79
A processor uses $\text{2-level}$ page tables for virtual to physical address translation. Page tables for both levels are stored in the main memory. Virtual and physical addresses are both $32$ bits wide. The memory is byte addressable. For virtual to physical address translation, ... tables of this process is $\text{8 KB}$ $\text{12 KB}$ $\text{16 KB}$ $\text{20 KB}$
A processor uses $\text{2-level}$ page tables for virtual to physical address translation. Page tables for both levels are stored in the main memory. Virtual and physical...
go_editor
24.0k
views
go_editor
asked
Apr 24, 2016
Operating System
gatecse-2003
operating-system
normal
virtual-memory
+
–
93
votes
10
answers
16
GATE CSE 2007 | Question: 80
Consider a machine with a byte addressable main memory of $2^{16}$ bytes. Assume that a direct mapped data cache consisting of $32$ lines of $64$ bytes each is used in the system. A $50 \times 50$ two-dimensional array of bytes is stored in the main ... data cache do not change in between the two accesses. How many data misses will occur in total? $48$ $50$ $56$ $59$
Consider a machine with a byte addressable main memory of $2^{16}$ bytes. Assume that a direct mapped data cache consisting of $32$ lines of $64$ bytes each is used in th...
Kathleen
32.6k
views
Kathleen
asked
Sep 21, 2014
CO and Architecture
gatecse-2007
co-and-architecture
cache-memory
normal
+
–
67
votes
6
answers
17
GATE CSE 2017 Set 2 | Question: 29
In a two-level cache system, the access times of $L_1$ and $L_2$ caches are $1$ and $8$ clock cycles, respectively. The miss penalty from the $L_2$ cache to main memory is $18$ clock cycles. The miss rate of $L_1$ cache is twice that of $L_2$. The average ... respectively are $0.111$ and $0.056$ $0.056$ and $0.111$ $0.0892$ and $0.1784$ $0.1784$ and $0.0892$
In a two-level cache system, the access times of $L_1$ and $L_2$ caches are $1$ and $8$ clock cycles, respectively. The miss penalty from the $L_2$ cache to main memory i...
Arjun
28.7k
views
Arjun
asked
Feb 14, 2017
CO and Architecture
gatecse-2017-set2
cache-memory
co-and-architecture
normal
+
–
69
votes
6
answers
18
GATE CSE 2014 Set 3 | Question: 44
The memory access time is $1$ nanosecond for a read operation with a hit in cache, $5$ nanoseconds for a read operation with a miss in cache, $2$ nanoseconds for a write operation with a hit in cache and $10$ nanoseconds for a write ... cache hit-ratio is $0.9$. The average memory access time (in nanoseconds) in executing the sequence of instructions is ______.
The memory access time is $1$ nanosecond for a read operation with a hit in cache, $5$ nanoseconds for a read operation with a miss in cache, $2$ nanoseconds for a write ...
go_editor
24.1k
views
go_editor
asked
Sep 28, 2014
CO and Architecture
gatecse-2014-set3
co-and-architecture
cache-memory
numerical-answers
normal
+
–
72
votes
6
answers
19
GATE CSE 2014 Set 2 | Question: 55
Consider the main memory system that consists of $8$ memory modules attached to the system bus, which is one word wide. When a write request is made, the bus is occupied for $100$ nanoseconds (ns) by the data, address, and control signals. ... bus at any time. The maximum number of stores (of one word each) that can be initiated in $1$ millisecond is ________
Consider the main memory system that consists of $8$ memory modules attached to the system bus, which is one word wide. When a write request is made, the bus is occupied ...
go_editor
27.0k
views
go_editor
asked
Sep 28, 2014
Operating System
gatecse-2014-set2
operating-system
memory-management
numerical-answers
normal
+
–
46
votes
3
answers
20
GATE CSE 2006 | Question: 62, ISRO2016-50
A CPU generates $32$-bit virtual addresses. The page size is $4$ KB. The processor has a translation look-aside buffer (TLB) which can hold a total of $128$ page table entries and is $4$-way set associative. The minimum size of the TLB tag is: $\text{11 bits}$ $\text{13 bits}$ $\text{15 bits}$ $\text{20 bits}$
A CPU generates $32$-bit virtual addresses. The page size is $4$ KB. The processor has a translation look-aside buffer (TLB) which can hold a total of $128$ page table en...
Rucha Shelke
25.9k
views
Rucha Shelke
asked
Sep 26, 2014
Operating System
gatecse-2006
operating-system
virtual-memory
normal
isro2016
+
–
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