Search results for pipelining / GATE Overflow for GATE CSE

97 votes

9 answers

1

GATE CSE 2013 | Question: 45
Consider an instruction pipeline with five stages without any branch prediction: Fetch Instruction (FI), Decode Instruction (DI), Fetch Operand (FO), Execute Instruction (EI) and Write Operand (WO). The stage delays for FI, DI, FO, EI and WO are ... during the execution of this program, the time (in ns) needed to complete the program is $132$ $165$ $176$ $328$

Consider an instruction pipeline with five stages without any branch prediction:Fetch Instruction (FI), Decode Instruction (DI), Fetch Operand (FO), Execute Instruction (...

Kriss Singh

47.8k views

Kriss Singh asked Sep 5, 2014

70 votes

5 answers

2

GATE CSE 2015 Set 3 | Question: 51
Consider the following reservation table for a pipeline having three stages $S_1, S_2 \text{ and } S_3$ ... $} & & & \text{$X$} & \\\hline \end{array}$ The minimum average latency (MAL) is ______

Consider the following reservation table for a pipeline having three stages $S_1, S_2 \text{ and } S_3$.$$\begin{array}{|ccccc|} \hline \textbf{Time} \rightarrow \\\hline...

go_editor

41.0k views

go_editor asked Feb 16, 2015

142 votes

4 answers

3

GATE CSE 2005 | Question: 68
A $5$ stage pipelined CPU has the following sequence of stages: IF - instruction fetch from instruction memory RD - Instruction decode and register read EX - Execute: ALU operation for data and address computation MA - Data memory access - for write access, the ... taken to complete the above sequence of instructions starting from the fetch of $I_1$? $8$ $10$ $12$ $15$

A $5$ stage pipelined CPU has the following sequence of stages:IF – instruction fetch from instruction memoryRD – Instruction decode and register readEX – Execute: ...

Kathleen

46.2k views

Kathleen asked Sep 22, 2014

52 votes

10 answers

4

GATE CSE 2009 | Question: 28
Consider a $4$ stage pipeline processor. The number of cycles needed by the four instructions $I1, I2, I3, I4$ in stages $S1, S2, S3, S4$ ... the number of cycles needed to execute the following loop? For (i=1 to 2) {I1; I2; I3; I4;} $16$ $23$ $28$ $30$

Consider a $4$ stage pipeline processor. The number of cycles needed by the four instructions $I1, I2, I3, I4$ in stages $S1, S2, S3, S4$ is shown below:$$\begin{array}{|...

Kathleen

34.3k views

Kathleen asked Sep 22, 2014

55 votes

2 answers

5

GATE CSE 2008 | Question: 36
Which of the following are NOT true in a pipelined processor? Bypassing can handle all RAW hazards Register renaming can eliminate all register carried WAR hazards Control hazard penalties can be eliminated by dynamic branch prediction I and II only I and III only II and III only I, II and III

Which of the following are NOT true in a pipelined processor?Bypassing can handle all RAW hazardsRegister renaming can eliminate all register carried WAR hazardsControl h...

Kathleen

22.1k views

Kathleen asked Sep 12, 2014

25 votes

4 answers

6

GATE CSE 2020 | Question: 43
Consider a non-pipelined processor operating at $2.5$ GHz. It takes $5$ clock cycles to complete an instruction. You are going to make a $5$- stage pipeline out of this processor. Overheads associated with pipelining force you to ... , the speedup achieved by the pipelined processor over the non-pipelined processor (round off to $2$ decimal places) is_____________.

Consider a non-pipelined processor operating at $2.5$ GHz. It takes $5$ clock cycles to complete an instruction. You are going to make a $5$- stage pipeline out of this p...

Arjun

16.4k views

Arjun asked Feb 12, 2020

56 votes

5 answers

7

GATE CSE 2015 Set 1 | Question: 38
Consider a non-pipelined processor with a clock rate of $2.5$ gigahertz and average cycles per instruction of four. The same processor is upgraded to a pipelined processor with five stages; but due to the internal pipeline delay, ... $2$ gigahertz. Assume that there are no stalls in the pipeline. The speedup achieved in this pipelined processor is_______________.

Consider a non-pipelined processor with a clock rate of $2.5$ gigahertz and average cycles per instruction of four. The same processor is upgraded to a pipelined processo...

makhdoom ghaya

29.9k views

makhdoom ghaya asked Feb 13, 2015

60 votes

8 answers

8

GATE CSE 2018 | Question: 50
The instruction pipeline of a RISC processor has the following stages: Instruction Fetch $(IF)$, Instruction Decode $(ID)$, Operand Fetch $(OF)$, Perform Operation $(PO)$ and Writeback $(WB)$, The $IF$, $ID$, $OF$ and $WB$ ... no data hazards and no control hazards. The number of clock cycles required for completion of execution of the sequence of instruction is _____.

The instruction pipeline of a RISC processor has the following stages: Instruction Fetch $(IF)$, Instruction Decode $(ID)$, Operand Fetch $(OF)$, Perform Operation $(PO)$...

gatecse

23.8k views

gatecse asked Feb 14, 2018

64 votes

3 answers

9

GATE CSE 2008 | Question: 76
Delayed branching can help in the handling of control hazards For all delayed conditional branch instructions, irrespective of whether the condition evaluates to true or false, The instruction following the conditional branch instruction in memory is ... The first instruction in the taken path is executed The branch takes longer to execute than any other instruction

Delayed branching can help in the handling of control hazardsFor all delayed conditional branch instructions, irrespective of whether the condition evaluates to true or f...

Kathleen

17.9k views

Kathleen asked Sep 12, 2014

73 votes

8 answers

10

GATE CSE 2016 Set 1 | Question: 32
The stage delays in a $4$-stage pipeline are $800, 500, 400$ and $300$ picoseconds. The first stage (with delay $800$ picoseconds) is replaced with a functionality equivalent design involving two stages with respective delays $600$ and $350$ picoseconds. The throughput increase of the pipeline is ___________ percent.

The stage delays in a $4$-stage pipeline are $800, 500, 400$ and $300$ picoseconds. The first stage (with delay $800$ picoseconds) is replaced with a functionality equiva...

Sandeep Singh

25.7k views

Sandeep Singh asked Feb 12, 2016

23 votes

4 answers

11

GATE CSE 2021 Set 2 | Question: 53
Consider a pipelined processor with $5$ stages, $\text{Instruction Fetch} (\textsf{IF})$, $\text{Instruction Decode} \textsf{(ID)}$, $\text{Execute } \textsf{(EX)}$, $\text{Memory Access } \textsf{(MEM)}$ ... $\textit{Speedup} $ achieved in executing the given instruction sequence on the pipelined processor (rounded to $2$ decimal places) is _____________

Consider a pipelined processor with $5$ stages, $\text{Instruction Fetch} (\textsf{IF})$, $\text{Instruction Decode} \textsf{(ID)}$, $\text{Execute } \textsf{(EX)}$, $\te...

Arjun

15.3k views

Arjun asked Feb 18, 2021

75 votes

8 answers

12

GATE CSE 2016 Set 2 | Question: 33
Consider a $3 \ \text{GHz}$ (gigahertz) processor with a three stage pipeline and stage latencies $\large\tau_1,\tau_2$ and $\large\tau_3$ such that $\large\tau_1 =\dfrac{3 \tau_2}{4}=2\tau_3$. If the longest pipeline stage is split into two pipeline stages of equal latency , the new frequency is __________ $\text{GHz}$, ignoring delays in the pipeline registers.

Consider a $3 \ \text{GHz}$ (gigahertz) processor with a three stage pipeline and stage latencies $\large\tau_1,\tau_2$ and $\large\tau_3$ such that $\large\tau_1 =\dfrac...

Akash Kanase

19.2k views

Akash Kanase asked Feb 12, 2016

45 votes

5 answers

13

GATE IT 2006 | Question: 79
A pipelined processor uses a 4-stage instruction pipeline with the following stages: Instruction fetch (IF), Instruction decode (ID), Execute (EX) and Writeback (WB). The arithmetic operations as well as the load and store operations are carried out in the EX ... is used. The number of clock cycles required to complete the sequence of instructions is $10$ $12$ $14$ $16$

A pipelined processor uses a 4-stage instruction pipeline with the following stages: Instruction fetch (IF), Instruction decode (ID), Execute (EX) and Writeback (WB). The...

Ishrat Jahan

17.3k views

Ishrat Jahan asked Nov 1, 2014

50 votes

9 answers

14

GATE CSE 2014 Set 1 | Question: 43
Consider a $6$-stage instruction pipeline, where all stages are perfectly balanced. Assume that there is no cycle-time overhead of pipelining. When an application is executing on this $6$-stage pipeline, the speedup achieved with respect to non-pipelined execution if $25$% of the instructions incur $2$ pipeline stall cycles is ____________

Consider a $6$-stage instruction pipeline, where all stages are perfectly balanced. Assume that there is no cycle-time overhead of pipelining. When an application is exec...

go_editor

20.0k views

go_editor asked Sep 28, 2014

49 votes

7 answers

15

GATE CSE 2008 | Question: 77
Delayed branching can help in the handling of control hazards The following code is to run on a pipelined processor with one branch delay slot: I1: ADD $R2 \leftarrow R7 + R8$ I2: Sub $R4 \leftarrow R5 – R6$ ... Which of the instructions I1, I2, I3 or I4 can legitimately occupy the delay slot without any program modification? I1 I2 I3 I4

Delayed branching can help in the handling of control hazardsThe following code is to run on a pipelined processor with one branch delay slot:I1: ADD $R2 \leftarrow R7 + ...

go_editor

15.3k views

go_editor asked Apr 23, 2016

50 votes

9 answers

16

GATE CSE 2006 | Question: 42
A CPU has a five-stage pipeline and runs at $1$ GHz frequency. Instruction fetch happens in the first stage of the pipeline. A conditional branch instruction computes the target address and evaluates the condition in the third stage of the pipeline. The processor stops fetching new ... : $\text{1.0 second}$ $\text{1.2 seconds}$ $\text{1.4 seconds}$ $\text{1.6 seconds}$

A CPU has a five-stage pipeline and runs at $1$ GHz frequency. Instruction fetch happens in the first stage of the pipeline. A conditional branch instruction computes the...

Rucha Shelke

21.1k views

Rucha Shelke asked Sep 26, 2014

9 votes

4 answers

17

GATE CSE 2023 | Question: 23
Consider a $3$-stage pipelined processor having a delay of $10 \mathrm{~ns}$ (nanoseconds), $20 \mathrm{~ns}$, and $14 \mathrm{~ns},$ for the first, second, and the third stages, respectively. Assume that there is no other ... instruction is fetched every cycle. The total execution time for executing $100$ instructions on this processor is _____________ $\mathrm{ns}.$

Consider a $3$-stage pipelined processor having a delay of $10 \mathrm{~ns}$ (nanoseconds), $20 \mathrm{~ns}$, and $14 \mathrm{~ns},$ for the first, second, and the third...

admin

9.3k views

admin asked Feb 15, 2023

46 votes

3 answers

18

GATE CSE 2015 Set 3 | Question: 47
Consider the following code sequence having five instructions from $I_1 \text{ to } I_5$. Each of these instructions has the following format. OP Ri, Rj, Rk Where operation OP is performed on contents of registers Rj and Rk and the result is stored in ... statements is/are correct? Only S1 is true Only S2 is true Only S1 and S3 are true Only S2 and S3 are true

Consider the following code sequence having five instructions from $I_1 \text{ to } I_5$. Each of these instructions has the following format. OP Ri, Rj, RkWhere operatio...

go_editor

21.9k views

go_editor asked Feb 15, 2015

44 votes

8 answers

19

GATE CSE 2017 Set 1 | Question: 50
Instruction execution in a processor is divided into $5$ stages, Instruction Fetch (IF), Instruction Decode (ID), Operand fetch (OF), Execute (EX), and Write Back (WB). These stages take 5, 4, 20, 10 and 3 nanoseconds (ns) ... speedup (correct to two decimal places) achieved by EP over NP in executing $20$ independent instructions with no hazards is _________ .

Instruction execution in a processor is divided into $5$ stages, Instruction Fetch (IF), Instruction Decode (ID), Operand fetch (OF), Execute (EX), and Write Back (WB). T...

khushtak

19.1k views

khushtak asked Feb 14, 2017

18 votes

5 answers

20

GATE CSE 2022 | Question: 51
A processor $\text{X}_{1}$ operating at $2 \; \text{GHz}$ has a standard $5-$stage $\text{RISC}$ instruction pipeline having a base $\text{CPI (cycles per instruction)}$ of one without any pipeline hazards. For a given program $\text{P}$ ... $\text{X}_{2}$ over $\text{X}_{1}$ in executing $\text{P}$ is _______________.

A processor $\text{X}_{1}$ operating at $2 \; \text{GHz}$ has a standard $5-$stage $\text{RISC}$ instruction pipeline having a base $\text{CPI (cycles per instruction)}$ ...

Arjun

10.0k views

Arjun asked Feb 15, 2022

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