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8085 is no longer in GATE syllabus but asked for ISRO and other exams

Recent questions tagged 8085

0 votes
1 answer
1
In 8085 microprocessor, what is the output of following program? LDA 8000H MVI B, 30H ADD B STA 800 H Read a number from input port and store it in memory Read a number from input device with address 8000H and store it in memory location 8001H Read a ... store it in memory location 8001H Load A with data from input device with address 8000H and display it on the output device with address 8001H
asked Jul 13, 2018 in CO and Architecture Pooja Khatri 305 views
0 votes
1 answer
2
1.In 8085 microprocessor which of the following flag(s) is (are) affected by an arithmetic operation? (1)AC flag only (2)CY flag only (3)Z flag only (4)AC,CY,Z flags
asked Nov 6, 2017 in Digital Logic mahalakshmi r 1.5k views
1 vote
2 answers
3
In the architecture of $8085$ ... a-iv b-i c-ii a-iii b-iv c-ii a-ii b-iii c-i a-i b-ii c-iv
asked Nov 5, 2017 in CO and Architecture Arjun 743 views
1 vote
1 answer
4
In $8085$ microprocessor the address bus is of ___________ bits. $4$ $8$ $16$ $32$
asked Nov 5, 2017 in CO and Architecture Arjun 1.5k views
2 votes
1 answer
5
In $8085$ microprocessor which of the following flag(s) is (are) affected by an arithmetic operation? AC flag only CY flag Only Z flag Only AC, CY, Z flags
asked Nov 5, 2017 in CO and Architecture Arjun 370 views
2 votes
2 answers
6
Consider the following program fragment in assembly language: mov ax, 0h mov cx, 0A h do loop: dec ax loop doloop What is the value of $ax$ and $cx$ registers after the completion of the doloop ? $ax= FFF5 \: h$ and $cx=0 \:h$ $ax= FFF6 \: h$ and $cx=0 \: h$ $ax= FFF7 \: h$ and $cx=0A \:h$ $ax=FFF5 \: h$ and $cx=0A \: h$
asked Nov 5, 2017 in CO and Architecture Arjun 3.4k views
5 votes
1 answer
7
Consider the following assembly program fragment: stc mov al, 11010110b mov cl,2 rcl al,3 rol al, 4 shr al, cl mul cl The contents of the destination register $ax$ (in hexadecimal ) and the status of Carry Flag (CF) after the execution of above instructions, are: $ax =003CH; \: CF=0$ $ax=001EH; \: CF=0$ $ax=007BH; \: CF=1$ $ax=00B7H; \: CF=1$
asked Nov 5, 2017 in CO and Architecture Arjun 3k views
7 votes
3 answers
8
Which interrupt in 8085 Microprocessor is unmaskable? RST 5.5 RST 7.5 TRAP Both (a) and (b)
asked May 7, 2017 in CO and Architecture sh!va 2.4k views
0 votes
0 answers
9
if the number starts with a letter of the alphabet, you need to add a zero before it. For example, AB is entered as 0abh. WHY?
asked May 4, 2017 in Digital Logic Epsilon95 185 views
0 votes
0 answers
10
The complement Accumulator (CMA) instruction in 8085 processor on execution affects a)Zero flag b) Sign flag c) Overflow flag d) none of the above
asked Feb 27, 2017 in CO and Architecture sh!va 329 views
1 vote
1 answer
11
The register in 8085 that is used to keep track of the memory address of the next opcode to be run in the program is the: a) Stack Pointer b) Program Counter c) Accumulator d) Non of the above
asked Feb 27, 2017 in CO and Architecture sh!va 156 views
2 votes
1 answer
12
If the total number of states in the fetching and execution phases of an 8085 instruction is know to be 7, number of states in these machine cycles is divided as ________
asked Dec 10, 2016 in Others jothee 262 views
0 votes
0 answers
13
An 8085-based microcomputer consisting of 16 kbytes of ROM, 16kbytes of RAM and four 8-bit I/O ports is to be designed using RAM and ROM chips each of 2 kbytes capacity. The chip to be used for I/O ports realization consists of two 8-bit ports and requires four ... in the memory address space. The I/O locations are to occupy lower order I/O address space. Give memory map and I/O address map.
asked Dec 1, 2016 in CO and Architecture makhdoom ghaya 131 views
1 vote
1 answer
14
Which of the following in 8085 microprocessor performs $HL = HL + HL$ ? DAD D DAD H DAD B DAD SP
asked Sep 30, 2016 in CO and Architecture makhdoom ghaya 307 views
1 vote
1 answer
15
1 vote
2 answers
16
The content of the accumulator after the execution of the following 8085 assembly language program, is MVI A, 35H MOV B, A STC CMC RAR XRA B $00H$ $35H$ $EFH$ $2FH$
asked Sep 26, 2016 in CO and Architecture makhdoom ghaya 2.3k views
1 vote
1 answer
17
3 votes
1 answer
18
Which of the following $8085$ microprocessor hardware interrupt has the lowest priority? RST $6.5$ RST $7.5$ TRAP INTR
asked Aug 9, 2016 in Unknown Category jothee 3.3k views
2 votes
1 answer
19
The RST 7 instruction in 8085 microprocessor is equal to CALL 0010 H CALL 0034 H CALL 0038 H CALL 003C H
asked Jul 31, 2016 in CO and Architecture jothee 1.9k views
1 vote
1 answer
20
Specify the contents of the accumulator and the status of the $S, Z$ and $CY$ flags when $8085$ microprocessor performs addition of $87 H$ and $79 H$. $11, 1, 1, 1$ $10, 0, 1, 0$ $01, 1, 0, 0$ $00, 0, 1, 1$
asked Jul 24, 2016 in CO and Architecture makhdoom ghaya 2.6k views
1 vote
2 answers
21
How many times will the following loop be executed ? LXI B, 0007 H LOP : DCX B MOV A, B ORA C JNZ LOP $05$ $07$ $09$ $00$
asked Jul 24, 2016 in CO and Architecture makhdoom ghaya 2.4k views
0 votes
1 answer
22
Match the following $8085$ ... a b c d iv i iii ii iii ii i iv ii iii i iv ii iv i iii
asked Jul 24, 2016 in CO and Architecture makhdoom ghaya 1.1k views
1 vote
4 answers
23
Which of the following in 8085 microprocessor performs HL=HL+DE ? DAD D DAD H DAD B DAD SP
asked Jul 11, 2016 in CO and Architecture Sanjay Sharma 1.9k views
4 votes
2 answers
24
Consider the following Assembly language program MVIA 30 H ACI 30 H XRA A POP H After the execution of the above program, the contents of the accumulator will be 30 H 60 H 00 H contents of stack
asked Jun 12, 2016 in CO and Architecture jothee 2.2k views
3 votes
4 answers
25
The TRAP is one of the interrupts available in INTEL 8085. Which one of the following statements is true of TRAP ? it is level triggered it is negative edge triggered it is +ve edge triggered it is both +ve and -ve edges triggered
asked Jun 1, 2016 in CO and Architecture jaiganeshcse94 2.1k views
3 votes
5 answers
26
The contents of the flag register after execution of the following program by 8085 microprocessor will be Program SUB A MVI B,(01)$_H$ DCR B HLT (54)$_H$ (00)$_H$ (01)$_H$ (45)$_H$
asked May 17, 2016 in CO and Architecture kvkumar 5k views
0 votes
2 answers
27
asked May 3, 2016 in CO and Architecture Sanjay Sharma 536 views
0 votes
1 answer
28
asked May 3, 2016 in CO and Architecture Sanjay Sharma 160 views
3 votes
2 answers
29
In 8085 microprocessor, the ISR for handling trap interrupt is at which location? $3CH$ $34H$ $74H$ $24H$
asked Apr 27, 2016 in CO and Architecture makhdoom ghaya 2.8k views
4 votes
5 answers
30
How many number of times the instruction sequence below will loop before coming out of the loop? MOV AL, 00H A1: INC AL JNZ A1 1 255 256 Will not come out of the loop.
asked Apr 27, 2016 in CO and Architecture makhdoom ghaya 2.6k views
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