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Recent questions tagged addressing-modes
1
vote
4
answers
1
NIELIT 2016 MAR Scientist B - Section C: 9
A certain processor supports only the immediate and the direct addressing modes. Which of the following programming language features cannot be implemented on this processor? Pointers. Arrays. Records. All of these.
A certain processor supports only the immediate and the direct addressing modes. Which of the following programming language features cannot be implemented on this processor? Pointers. Arrays. Records. All of these.
asked
Mar 31, 2020
in
CO and Architecture
Lakshman Patel RJIT
572
views
nielit2016mar-scientistb
co-and-architecture
addressing-modes
0
votes
2
answers
2
NIELIT 2016 DEC Scientist B (IT) - Section B: 55
The example of implied addressing is Stack addressing Indirect addressing Immediate addressing None of the above
The example of implied addressing is Stack addressing Indirect addressing Immediate addressing None of the above
asked
Mar 31, 2020
in
CO and Architecture
Lakshman Patel RJIT
728
views
nielit2016dec-scientistb-it
co-and-architecture
addressing-modes
0
votes
2
answers
3
NIELIT 2016 DEC Scientist B (CS) - Section B: 53
The addressing mode used in an instruction of the form $ADD\:X\:Y$, is Direct Absolute Indirect Indexed
The addressing mode used in an instruction of the form $ADD\:X\:Y$, is Direct Absolute Indirect Indexed
asked
Mar 31, 2020
in
CO and Architecture
Lakshman Patel RJIT
446
views
nielit2016dec-scientistb-cs
co-and-architecture
addressing-modes
0
votes
3
answers
4
NIELIT 2017 DEC Scientist B - Section B: 40
Which of the following is/are not features of RISC processor? Large number of addressing modes. Uniform instruction set. (i) Only (ii) Only Both (i) and (ii) None of the options
Which of the following is/are not features of RISC processor? Large number of addressing modes. Uniform instruction set. (i) Only (ii) Only Both (i) and (ii) None of the options
asked
Mar 30, 2020
in
CO and Architecture
Lakshman Patel RJIT
1.3k
views
nielit2017dec-scientistb
co-and-architecture
addressing-modes
instruction-format
0
votes
4
answers
5
NIELIT 2017 DEC Scientist B - Section B: 47
INCA(Increase register A by $1$) is an example of which of the following addressing mode? Immediate addressing Indirect addressing Implied addressing Relative addressing
INCA(Increase register A by $1$) is an example of which of the following addressing mode? Immediate addressing Indirect addressing Implied addressing Relative addressing
asked
Mar 30, 2020
in
CO and Architecture
Lakshman Patel RJIT
947
views
nielit2017dec-scientistb
co-and-architecture
addressing-modes
0
votes
2
answers
6
NIELIT 2017 DEC Scientist B - Section B: 59
A two-word instruction is stored in a location $A$. The operand part of instruction holds $B$. If the addressing mode is relative, the operand is available in location $A+B+2$ $A+B+1$ $B+1$ $A+B$
A two-word instruction is stored in a location $A$. The operand part of instruction holds $B$. If the addressing mode is relative, the operand is available in location $A+B+2$ $A+B+1$ $B+1$ $A+B$
asked
Mar 30, 2020
in
CO and Architecture
Lakshman Patel RJIT
549
views
nielit2017dec-scientistb
co-and-architecture
addressing-modes
0
votes
2
answers
7
UGCNET-Jan2017-III: 4
Match the following ... iii, c-i, d-ii a-iv, b-i, c-iii, d-ii a-iv, b-ii, c-i, d-iii a-iv, b-iii, c-ii, d-i
Match the following ... a-iv, b-iii, c-i, d-ii a-iv, b-i, c-iii, d-ii a-iv, b-ii, c-i, d-iii a-iv, b-iii, c-ii, d-i
asked
Mar 24, 2020
in
CO and Architecture
jothee
297
views
ugcnetjan2017iii
co-and-architecture
addressing-modes
2
votes
4
answers
8
ISRO2020-15
A stack organized computer is characterised by instructions with indirect addressing direct addressing zero addressing index addressing
A stack organized computer is characterised by instructions with indirect addressing direct addressing zero addressing index addressing
asked
Jan 13, 2020
in
CO and Architecture
Satbir
1.3k
views
isro-2020
co-and-architecture
addressing-modes
normal
1
vote
3
answers
9
ISRO2020-1
The immediate addressing mode can be used for Loading internal registers with initial values Perform arithmetic or logical operation on data contained in instructions Which of the following is true? Only $1$ Only $2$ Both $1$ and $2$ Immediate mode refers to data in cache
The immediate addressing mode can be used for Loading internal registers with initial values Perform arithmetic or logical operation on data contained in instructions Which of the following is true? Only $1$ Only $2$ Both $1$ and $2$ Immediate mode refers to data in cache
asked
Jan 13, 2020
in
CO and Architecture
Satbir
670
views
isro-2020
co-and-architecture
normal
addressing-modes
4
votes
2
answers
10
ISRO2020-8
Consider a $32$- bit processor which supports $70$ instructions. Each instruction is $32$ bit long and has $4$ fields namely opcode, two register identifiers and an immediate operand of unsigned integer type. Maximum value of the immediate operand that can be supported by the processor is $8191$. How many registers the processor has? $32$ $64$ $128$ $16$
Consider a $32$- bit processor which supports $70$ instructions. Each instruction is $32$ bit long and has $4$ fields namely opcode, two register identifiers and an immediate operand of unsigned integer type. Maximum value of the immediate operand that can be supported by the processor is $8191$. How many registers the processor has? $32$ $64$ $128$ $16$
asked
Jan 13, 2020
in
CO and Architecture
Satbir
1k
views
isro-2020
co-and-architecture
addressing-modes
normal
4
votes
4
answers
11
UGCNET-June-2019-II: 11
Which type of addressing mode, less number of memory references are required? Immediate Implied Register Indexed
Which type of addressing mode, less number of memory references are required? Immediate Implied Register Indexed
asked
Jul 2, 2019
in
CO and Architecture
Arjun
2.8k
views
ugcnetjune2019ii
addressing-modes
0
votes
2
answers
12
machine instructions and addressing modes
A digital computer has memory unit with $24$ bits word.The instruction set consists of $150$ different operations. All instructions have an operation code part and an address part. Each instruction is stored in one word of memory. $Q1$ How many bits are needed for the OP-CODE and ... $2^{16}, 2^{24}$ $2^{16},2^{24}-1$ $\textrm{None of these}$
A digital computer has memory unit with $24$ bits word.The instruction set consists of $150$ different operations. All instructions have an operation code part and an address part. Each instruction is stored in one word of memory. $Q1$ How many bits are needed for the OP-CODE and how many bit are left for the ... $2^{16}, 2^{24}$ $2^{16},2^{24}-1$ $\textrm{None of these}$
asked
May 24, 2019
in
CO and Architecture
Gitika Babbar
824
views
co-and-architecture
addressing-modes
0
votes
1
answer
13
Self doubt
Can anyone please explain in simple terms indexed, relative and base register addressing modes?
Can anyone please explain in simple terms indexed, relative and base register addressing modes?
asked
Jan 19, 2019
in
CO and Architecture
subho16
163
views
addressing-modes
computer-architecture
1
vote
1
answer
14
What is mean by "Index Value" in Indexed Addressing Mode?
If someone mentioned "index value" in indexed addressing mode then which value is it referring; the value of index register or the constant value? It should be value of index register, isn't it? But from the given snippet it seems that they are referring constant value Please clarify Thank You
If someone mentioned "index value" in indexed addressing mode then which value is it referring; the value of index register or the constant value? It should be value of index register, isn't it? But from the given snippet it seems that they are referring constant value Please clarify Thank You
asked
Jan 8, 2019
in
CO and Architecture
newbie
420
views
co-and-architecture
addressing-modes
1
vote
1
answer
15
Indirect index addressing mode
I know about indirect addressing mode , Index addressing mode but do not know about Indirect index addressing mode ? in one solution of a question they told that Indirect index addressing mode does not add some constant value (base address etc ) while calculating the effective address i did not found it on google etc explain Indirect index addressing mode
I know about indirect addressing mode , Index addressing mode but do not know about Indirect index addressing mode ? in one solution of a question they told that Indirect index addressing mode does not add some constant value (base address etc ) while calculating the effective address i did not found it on google etc explain Indirect index addressing mode
asked
Jan 4, 2019
in
CO and Architecture
Gurdeep Saini
338
views
co-and-architecture
addressing-modes
0
votes
3
answers
16
MadeEasy Test Series: CO & Architecture - Addressing Modes
The Data transfer instruction size is $64-bit$ ALU, ALU operation instruction size is $32-bit$ and branch instruction size is $16-bit$. Assume program has been loaded in the memory starting from address 3000 decimal. If an ... executing, PC value will be 3030, but given answer is 3028 Previous Q: https://gateoverflow.in/1058/gate2004-63
The Data transfer instruction size is $64-bit$ ALU, ALU operation instruction size is $32-bit$ and branch instruction size is $16-bit$. Assume program has been loaded in the memory starting from address 3000 decimal. If an interrupt occurs during the execution of $I-6$, ... When $I-6$ is executing, PC value will be 3030, but given answer is 3028 Previous Q: https://gateoverflow.in/1058/gate2004-63
asked
Dec 27, 2018
in
CO and Architecture
Learner_jai
750
views
co-and-architecture
made-easy-test-series
addressing-modes
0
votes
1
answer
17
NTA NET DEC 2018 Q44
asked
Dec 25, 2018
in
CO and Architecture
Sanjay Sharma
239
views
addressing-modes
0
votes
1
answer
18
Testbook Test Series: CO & Architecture - Addressing Modes
A PC-related mode branch instruction is $8$Byte long. The address of the instruction,in decimal, is $548321.$Find the branch target address if the signed displacement in the instruction is $-29?$
A PC-related mode branch instruction is $8$Byte long. The address of the instruction,in decimal, is $548321.$Find the branch target address if the signed displacement in the instruction is $-29?$
asked
Dec 23, 2018
in
CO and Architecture
Lakshman Patel RJIT
340
views
co-and-architecture
testbook-test-series
addressing-modes
1
vote
3
answers
19
NIELIT 2018-82
Identify the true statement from the given statements. Program relocation at run time requires transfer complete block to some memory locations requires both base address and relative address requires only absolute address $1$ $1$ and $2$ $1$ , $2$ and $3$ $1$ and $3$
Identify the true statement from the given statements. Program relocation at run time requires transfer complete block to some memory locations requires both base address and relative address requires only absolute address $1$ $1$ and $2$ $1$ , $2$ and $3$ $1$ and $3$
asked
Dec 7, 2018
in
CO and Architecture
Arjun
737
views
nielit-2018
co-and-architecture
addressing-modes
0
votes
2
answers
20
Memory Access-self doubt
what is the number of memory accessed required in register indirect mode index register mode base register mode pls explain in details with examples
what is the number of memory accessed required in register indirect mode index register mode base register mode pls explain in details with examples
asked
Nov 30, 2018
in
CO and Architecture
aditi19
196
views
co-and-architecture
addressing-modes
effective-memory-access
5
votes
1
answer
21
Addressing Mode
Consider we have an instruction Load 1000. Given Memory and Register R1 as Follows. What is the actual value Loaded in the accumulator ? A. 1000 1400 1300 1000 B. 1400 1300 1000 1000 C. 1000 1300 1400 1000 D. 1300 1000 1400 1000
Consider we have an instruction Load 1000. Given Memory and Register R1 as Follows. What is the actual value Loaded in the accumulator ? A. 1000 1400 1300 1000 B. 1400 1300 1000 1000 C. 1000 1300 1400 1000 D. 1300 1000 1400 1000
asked
Oct 12, 2018
in
CO and Architecture
Na462
809
views
addressing-modes
co-and-architecture
instruction-format
1
vote
1
answer
22
TESTBOOK TEST SERIES
A register to register machine supports 2-address. 1-address and zero-address instructions instruction register size is 24 bits and register set size is 480. If there are 48 2-address instructions and 2048 Zero - address instructions then what is the maximum possible number of 1 - address instruction?
A register to register machine supports 2-address. 1-address and zero-address instructions instruction register size is 24 bits and register set size is 480. If there are 48 2-address instructions and 2048 Zero - address instructions then what is the maximum possible number of 1 - address instruction?
asked
Sep 30, 2018
in
CO and Architecture
Avik Chowdhury
340
views
addressing-modes
1
vote
0
answers
23
self doubt
How stack addressing is related to Reentranecy ,can anyone explain it?
How stack addressing is related to Reentranecy ,can anyone explain it?
asked
Sep 27, 2018
in
CO and Architecture
Prince Sindhiya
109
views
co-and-architecture
addressing-modes
0
votes
0
answers
24
Self Doubt on GATE2005-65
https://gateoverflow.in/1388/gate2005-65 $\text{In this question, what will be the number of }$ $\textbf{cycles}$ $\text{needed during execution cycle of instruction}$ $\text{According to me I am getting 6 cycles. Please tell what could be the correct answer for it}$
https://gateoverflow.in/1388/gate2005-65 $\text{In this question, what will be the number of }$ $\textbf{cycles}$ $\text{needed during execution cycle of instruction}$ $\text{According to me I am getting 6 cycles. Please tell what could be the correct answer for it}$
asked
Sep 10, 2018
in
CO and Architecture
!KARAN
350
views
usergate2005
usermod
co-and-architecture
addressing-modes
0
votes
1
answer
25
Addressing Instructions
Are memory to memory instructions allowed? Eg. ADD [123], [345] or MOV [123], [343] If not, then why?
Are memory to memory instructions allowed? Eg. ADD [123], [345] or MOV [123], [343] If not, then why?
asked
Sep 6, 2018
in
CO and Architecture
Asutosh
200
views
co-and-architecture
addressing-modes
7
votes
0
answers
26
Addressing Mode
Addressing Mode. Instruction Meaning Description $1.$Register Addressing Mode (or) Register Direct AM $\text{Add} R_{1},R_{2}$ $R_{1}\leftarrow R_{1}+R_{2}$ ... ? Plz check https://www.slideshare.net/aliasgharmanjotho11/addressing-modes-37108170 http://web.cs.iastate.edu/~prabhu/Tutorial/PIPELINE/addressMode.html
Addressing Mode. Instruction Meaning Description $1.$Register Addressing Mode (or) Register Direct AM $\text{Add} R_{1},R_{2}$ $R_{1}\leftarrow R_{1}+R_{2}$ Two General Purpose Register value is added. Operands stored in GPRs $2.$ ... missing? Plz check https://www.slideshare.net/aliasgharmanjotho11/addressing-modes-37108170 http://web.cs.iastate.edu/~prabhu/Tutorial/PIPELINE/addressMode.html
asked
Aug 28, 2018
in
CO and Architecture
srestha
865
views
addressing-modes
co-and-architecture
2
votes
0
answers
27
Addressing modes
Instructions are stored in memory. When they are to be executed they are brought into instruction register. Now it is divided as Mode, opcode, operand (log (memory size) is divided in three parts) . In direct addressing, operand represent the effective ... required to address a memory then how such a big instruction is stored in memory whose operand itself has those many bits?
Instructions are stored in memory. When they are to be executed they are brought into instruction register. Now it is divided as Mode, opcode, operand (log (memory size) is divided in three parts) . In direct addressing, operand represent the effective memory address ... bits required to address a memory then how such a big instruction is stored in memory whose operand itself has those many bits?
asked
Aug 15, 2018
in
CO and Architecture
tusharp
341
views
addressing-modes
co-and-architecture
3
votes
2
answers
28
Instruction Addressing
A computer has 170 different operations. Word size is 4 bytes one word instructions requires two address fields. One address for register and one address for memory. If there are 37 registers then the memory size is ______________(in KB). Ans. 256KB
A computer has 170 different operations. Word size is 4 bytes one word instructions requires two address fields. One address for register and one address for memory. If there are 37 registers then the memory size is ______________(in KB). Ans. 256KB
asked
Jul 31, 2018
in
CO and Architecture
Na462
931
views
co-and-architecture
addressing-modes
machine-instructions
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