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Recent questions tagged addressing-modes

0 votes
2 answers
1
Which of the following is/are not features of RISC processor? Large number of addressing modes. Uniform instruction set. (i) Only (ii) Only Both (i) and (ii) None of the options
asked Mar 30 in CO and Architecture Lakshman Patel RJIT 203 views
0 votes
3 answers
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INCA(Increase register A by $1$) is an example of which of the following addressing mode? Immediate addressing Indirect addressing Implied addressing Relative addressing
asked Mar 30 in CO and Architecture Lakshman Patel RJIT 159 views
0 votes
2 answers
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A two-word instruction is stored in a location $A$. The operand part of instruction holds $B$. If the addressing mode is relative, the operand is available in location $A+B+2$ $A+B+1$ $B+1$ $A+B$
asked Mar 30 in CO and Architecture Lakshman Patel RJIT 124 views
2 votes
3 answers
5
A stack organized computer is characterised by instructions with indirect addressing direct addressing zero addressing index addressing
asked Jan 13 in CO and Architecture Satbir 591 views
1 vote
1 answer
6
The immediate addressing mode can be used for Loading internal registers with initial values Perform arithmetic or logical operation on data contained in instructions Which of the following is true? Only $1$ Only $2$ Both $1$ and $2$ Immediate mode refers to data in cache
asked Jan 13 in CO and Architecture Satbir 332 views
4 votes
2 answers
7
Consider a $32$- bit processor which supports $70$ instructions. Each instruction is $32$ bit long and has $4$ fields namely opcode, two register identifiers and an immediate operand of unsigned integer type. Maximum value of the immediate operand that can be supported by the processor is $8191$. How many registers the processor has? $32$ $64$ $128$ $16$
asked Jan 13 in CO and Architecture Satbir 524 views
4 votes
4 answers
8
Which type of addressing mode, less number of memory references are required? Immediate Implied Register Indexed
asked Jul 2, 2019 in CO and Architecture Arjun 1.3k views
0 votes
2 answers
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A digital computer has memory unit with $24$ bits word.The instruction set consists of $150$ different operations. All instructions have an operation code part and an address part. Each instruction is stored in one word of memory. $Q1$ How many bits are needed for the OP-CODE and how many bit are left for the ... $2^{16}, 2^{24}$ $2^{16},2^{24}-1$ $\textrm{None of these}$
asked May 24, 2019 in CO and Architecture Gitika Babbar 453 views
0 votes
1 answer
10
Can anyone please explain in simple terms indexed, relative and base register addressing modes?
asked Jan 19, 2019 in CO and Architecture subho16 125 views
1 vote
1 answer
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If someone mentioned "index value" in indexed addressing mode then which value is it referring; the value of index register or the constant value? It should be value of index register, isn't it? But from the given snippet it seems that they are referring constant value Please clarify Thank You
asked Jan 8, 2019 in CO and Architecture newbie 216 views
1 vote
1 answer
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I know about indirect addressing mode , Index addressing mode but do not know about Indirect index addressing mode ? in one solution of a question they told that Indirect index addressing mode does not add some constant value (base address etc ) while calculating the effective address i did not found it on google etc explain Indirect index addressing mode
asked Jan 4, 2019 in CO and Architecture Gurdeep Saini 221 views
0 votes
2 answers
13
The Data transfer instruction size is $64-bit$ ALU, ALU operation instruction size is $32-bit$ and branch instruction size is $16-bit$. Assume program has been loaded in the memory starting from address 3000 decimal. If an interrupt occurs during the execution of $I-6$, ... When $I-6$ is executing, PC value will be 3030, but given answer is 3028 Previous Q: https://gateoverflow.in/1058/gate2004-63
asked Dec 27, 2018 in CO and Architecture Learner_jai 414 views
0 votes
1 answer
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0 votes
1 answer
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A PC-related mode branch instruction is $8$Byte long. The address of the instruction,in decimal, is $548321.$Find the branch target address if the signed displacement in the instruction is $-29?$
asked Dec 23, 2018 in CO and Architecture Lakshman Patel RJIT 230 views
0 votes
2 answers
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what is the number of memory accessed required in register indirect mode index register mode base register mode pls explain in details with examples
asked Nov 30, 2018 in CO and Architecture aditi19 137 views
4 votes
1 answer
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Consider we have an instruction Load 1000. Given Memory and Register R1 as Follows. What is the actual value Loaded in the accumulator ? A. 1000 1400 1300 1000 B. 1400 1300 1000 1000 C. 1000 1300 1400 1000 D. 1300 1000 1400 1000
asked Oct 12, 2018 in CO and Architecture Na462 463 views
1 vote
1 answer
18
A register to register machine supports 2-address. 1-address and zero-address instructions instruction register size is 24 bits and register set size is 480. If there are 48 2-address instructions and 2048 Zero - address instructions then what is the maximum possible number of 1 - address instruction?
asked Sep 30, 2018 in CO and Architecture Avik Chowdhury 221 views
1 vote
0 answers
19
How stack addressing is related to Reentranecy ,can anyone explain it?
asked Sep 27, 2018 in CO and Architecture Prince Sindhiya 79 views
0 votes
0 answers
20
https://gateoverflow.in/1388/gate2005-65 $\text{In this question, what will be the number of }$ $\textbf{cycles}$ $\text{needed during execution cycle of instruction}$ $\text{According to me I am getting 6 cycles. Please tell what could be the correct answer for it}$
asked Sep 10, 2018 in CO and Architecture !KARAN 236 views
0 votes
0 answers
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Are memory to memory instructions allowed? Eg. ADD [123], [345] or MOV [123], [343] If not, then why?
asked Sep 6, 2018 in CO and Architecture Asutosh 140 views
6 votes
0 answers
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Addressing Mode. Instruction Meaning Description $1.$Register Addressing Mode (or) Register Direct AM $\text{Add} R_{1},R_{2}$ $R_{1}\leftarrow R_{1}+R_{2}$ Two General Purpose Register value is added. Operands stored in GPRs $2.$ ... missing? Plz check https://www.slideshare.net/aliasgharmanjotho11/addressing-modes-37108170 http://web.cs.iastate.edu/~prabhu/Tutorial/PIPELINE/addressMode.html
asked Aug 28, 2018 in CO and Architecture srestha 523 views
1 vote
0 answers
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Instructions are stored in memory. When they are to be executed they are brought into instruction register. Now it is divided as Mode, opcode, operand (log (memory size) is divided in three parts) . In direct addressing, operand represent the effective memory address ... bits required to address a memory then how such a big instruction is stored in memory whose operand itself has those many bits?
asked Aug 15, 2018 in CO and Architecture tusharp 245 views
3 votes
1 answer
24
A computer has 170 different operations. Word size is 4 bytes one word instructions requires two address fields. One address for register and one address for memory. If there are 37 registers then the memory size is ______________(in KB). Ans. 256KB
asked Jul 31, 2018 in CO and Architecture Na462 558 views
1 vote
1 answer
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1 vote
2 answers
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A system has 16 bits instruction that support zero address, one address and two address instructions Assume each address field size is 5 bits it is designed for supporting ‘40’ number of two address instructions, ‘400' number of one address instructions. The maximum number of zero address instructions that can be formulated is
asked May 11, 2018 in CO and Architecture Kartavya Kothari 278 views
1 vote
2 answers
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1 vote
1 answer
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Plz describe Which addressing mode does this following line represents and how? Index addressing mode, $X\left ( R_{1} \right )$, where $X$ is an offset represented in $2$'s complement $16$ bit representation
asked Apr 26, 2018 in CO and Architecture srestha 264 views
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