Recent questions tagged addressing-modes

+2 votes

1 answer

1

Addressing
branch address sign displacement -32. Can anybody explain this line with example? Do it mean target address can be 32 bit before branch address?

asked Oct 12 in CO & Architecture by srestha Veteran (65.2k points) | 51 views

+1 vote

1 answer

2

helpless mind
What is the difference between Base addressing and Index addressing? And finally how does based indexed addressing works?

asked Oct 11 in CO & Architecture by Warlock lord Active (1.7k points) | 48 views

+1 vote

1 answer

3

Register Direct and Indirect Addressing Mode

asked Sep 26 in CO & Architecture by Shubhanshu Boss (9.1k points) | 72 views

+3 votes

1 answer

4

Practice Question_Addressing Modes

asked Aug 7 in CO & Architecture by mystylecse Active (2.2k points) | 158 views

+1 vote

1 answer

5

addressing modes
A certain machine uses expanding opcode. It has 16-bit instructions and 6-bit addresses. It supports one address and two address instructions only. If there are ‘n’ two address instructions, the maximum number of one address instruction is (a) 2^16 – n (b) 2^10 – n (c) (2^4 – n) × 2^6 (d) 2^10

asked Aug 7 in CO & Architecture by Sunil8860 (261 points) | 116 views

+1 vote

0 answers

6

addressing mode
In base index addressing mode how many number of cycles for operand fetch is to be required? is it 8 ? Assume 4cycles =consumed for memory reference 2 cycle = consumed for arithmetic operations 1cycle =consumed when operand present in register 0 cycle = ... R2) R3 <- R3 + M[R1+R2] Useful in array addressing: R1 - base of array R2 - index amount

asked Jul 28 in CO & Architecture by set2018 Loyal (4.7k points) | 83 views

+2 votes

2 answers

7

morris mano addressing mode 3rd edition

asked Jul 28 in CO & Architecture by set2018 Loyal (4.7k points) | 121 views

+1 vote

1 answer

8

morris-mano addressing mode 3rd edition

asked Jul 28 in CO & Architecture by set2018 Loyal (4.7k points) | 84 views

+1 vote

1 answer

9

Addressing mode
Self reallocating code required for displacement addressing mode.How ?Please someone explain this concept.

asked Jul 17 in CO & Architecture by set2018 Loyal (4.7k points) | 77 views

+1 vote

1 answer

10

Addressing modes
Consider a 16 bit hypothetical process which support 1 word instruction , instruction contain 8 bit opcode ,and address field , instruction is stored in the memory with the starting address of 732, decimal on words . Processor contain 1 register ... 8) pc relative address mode 9) base relative address mode ro as base register . Explain each ans...

asked Jun 25 in CO & Architecture by sid1221 Active (2.1k points) | 108 views

+2 votes

3 answers

11

ISRO2017-19
The most appropriate matching for the following pairs: X: Indirect Addressing 1. Loop Y: Immediate Addressing 2. Pointers Z: Auto Decrement Addressing 3. Constants X-3 Y-2 Z-1 X-2 Y-3 Z-1 X- 3 Y-1 Z-2 X-2 Y-1 Z-3

asked May 7 in CO & Architecture by sh!va Veteran (30.2k points) | 833 views

+3 votes

3 answers

12

GATE2017-1-11
Consider the C struct defined below: struct data { int marks [100]; char grade; int cnumber; }; struct data student; The base address of student is available in register R1. The field student.grade can be accessed efficiently using (A) Post- ... , R1 (D) Index addressing mode, X(R1), where X is an offset represented in 2's complement 16-bit representation.

asked Feb 14 in CO & Architecture by Arjun Veteran (319k points) | 1.1k views

0 votes

0 answers

13

difference between registers which hold the address bits and which hold data bits

asked Jan 19 in CO & Architecture by khushtak Boss (7.6k points) | 109 views

+1 vote

1 answer

14

ace coa subject test
AFAIK "In direct we do specify the address of the operand right? Its just that we specify it in the instruction directly, ie hardcode the address in the instruction. In implied there is no address given since address is deduced from the operation itself." Is this right?

asked Jan 17 in CO & Architecture by Purple Loyal (4.1k points) | 69 views

0 votes

1 answer

15

COA: Addressing Modes
When we use auto increment or auto decrement addressing modes then which of the following is/are true? (i) In auto increment the operand is retrieved first and then the address altered. (ii) In auto decrement the address altered ... retrieve the operand. PS: given answer i and ii are correct. shouldn't it be mentioned pre/post increment/decrement

asked Jan 8 in CO & Architecture by Vijay Thakur Veteran (16.4k points) | 169 views

0 votes

0 answers

16

addressing mode

asked Jan 7 in CO & Architecture by vaishali jhalani Boss (6.5k points) | 86 views

+1 vote

1 answer

17

Addressing Mode
S1 : Relative mode is the addressing mode which can be used to write code in which reallocation is done at run time. S2 : Indirect addressing through registers can be used to access global variables. Which of the following option is correct?

asked Jan 7 in CO & Architecture by srestha Veteran (65.2k points) | 209 views

+2 votes

2 answers

18

GATE1989-2-ii
Match the pairs in the following questions: (A) Base addressing (p) Reentranecy (B) Indexed addressing (q) Accumulator (C) Stack addressing (r) Array (D) Implied addressing (s) Position independent

asked Nov 27, 2016 in CO & Architecture by makhdoom ghaya Veteran (39.8k points) | 301 views

+3 votes

1 answer

19

PC relative addressing mode
Here we will consider memory as word addressable or byte addressable?

asked Nov 23, 2016 in CO & Architecture by vaishali jhalani Boss (6.5k points) | 267 views

+5 votes

3 answers

20

GATE1987-1-V
The most relevant addressing mode to write position-independent codes is: Direct mode Indirect mode Relative mode Indexed mode

asked Nov 8, 2016 in CO & Architecture by makhdoom ghaya Veteran (39.8k points) | 555 views

+4 votes

2 answers

21

Addressing mode
What is the number of instrunctions needed to add n numbers in one address mode and store the result in the memory, assuming each number is already loaded in register? (A) n (B) n+1 (C) n-1 (D) 2n

asked Oct 30, 2016 in CO & Architecture by Rakesh K Active (1.9k points) | 357 views

0 votes

2 answers

22

Online

asked Oct 2, 2016 in CO & Architecture by Rahul Jain25 Veteran (12.2k points) | 148 views

0 votes

1 answer

23

UGCNET-Dec2013-III-49
Match the following: List-I List-II a. Indexed addressing i. is not used when an operand is moved from memory into a register or from a register to memory b. Direct addressing ii. Memory address is computed by adding up two registers plus an (optional) offset c. Register ... , b-iv, c-i, d-iii a-iii, b-iv, c-i, d-ii a-iii, b-i, c-iv, d-ii

asked Jul 29, 2016 in CO & Architecture by jothee Veteran (92.7k points) | 185 views

0 votes

1 answer

24

doubt regarding Addressing mode

asked Jul 21, 2016 in CO & Architecture by Don't you worry Active (1.9k points) | 145 views

+2 votes

4 answers

25

immediate Addressing

asked Jun 30, 2016 in CO & Architecture by himanich (389 points) | 674 views

0 votes

1 answer

26

Calculate effective memory address

asked Jun 16, 2016 in CO & Architecture by sh!va Veteran (30.2k points) | 214 views

+3 votes

3 answers

27

ISRO2009-21, UGCNET-Dec2012-II-12

asked Jun 3, 2016 in CO & Architecture by Desert_Warrior Boss (9.6k points) | 1k views

+2 votes

1 answer

28

CO: Addressing Modes
Consider 1GHz clock frequency processor, uses different operand access modes shown below: Assume that 8 cycle consumed for memory reference, 4 cycles consumed for arithmetic computation and 0 cycles consumed when the operand is in register instruction itself. What is ... ? 117.45 M words/sec 113.63 M words/sec 217.45 M words/sec 316.45 M words/sec

asked Jan 7, 2016 in CO & Architecture by Prasanna Loyal (4.4k points) | 352 views

+2 votes

3 answers

29

Addressing mode used by PC

asked Dec 4, 2015 in CO & Architecture by Himanshu1 Veteran (16.7k points) | 385 views

+1 vote

2 answers

30

memory addressing
Consider $1 \text{GHz}$ clock frequency processor,uses different operand accessing models shown below: Operand Accessing Mode Frequency(%) Register 10 Immediate 20 Direct 30 Memory Indirect 20 Indexed 20 Assume that $2$ memory cycles consumed for ... fetch rate (in millions $\text{words/sec}$) of processor is __________ (upto 2 to decimal places).

asked Nov 8, 2015 in CO & Architecture by Shefali Active (1.4k points) | 560 views

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