Recent questions tagged addressing-modes

Recent questions tagged addressing-modes

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Applied Test Series
An instruction is stored at location 300 with its address field at location 301. The address field has the value 400. A processor register R1 contains the number 200. Evaluate effective address if the addressing mode of the instruction is Index with R1 as the index register.

LRU asked in CO and Architecture Oct 24, 2021

by LRU

328 views

2 votes

5 answers

2

NIELIT 2016 MAR Scientist B - Section C: 9
A certain processor supports only the immediate and the direct addressing modes. Which of the following programming language features cannot be implemented on this processor? Pointers. Arrays. Records. All of these.

Lakshman Patel RJIT asked in CO and Architecture Mar 31, 2020

by Lakshman Patel RJIT

1.0k views

0 votes

3 answers

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NIELIT 2016 DEC Scientist B (IT) - Section B: 55
The example of implied addressing is Stack addressing Indirect addressing Immediate addressing None of the above

Lakshman Patel RJIT asked in CO and Architecture Mar 31, 2020

by Lakshman Patel RJIT

1.6k views

0 votes

2 answers

4

NIELIT 2016 DEC Scientist B (CS) - Section B: 53
The addressing mode used in an instruction of the form $ADD\:X\:Y$, is Direct Absolute Indirect Indexed

Lakshman Patel RJIT asked in CO and Architecture Mar 31, 2020

by Lakshman Patel RJIT

1.3k views

0 votes

3 answers

5

NIELIT 2017 DEC Scientist B - Section B: 40
Which of the following is/are not features of RISC processor? Large number of addressing modes. Uniform instruction set. (i) Only (ii) Only Both (i) and (ii) None of the options

Lakshman Patel RJIT asked in CO and Architecture Mar 30, 2020

by Lakshman Patel RJIT

3.4k views

1 vote

4 answers

6

NIELIT 2017 DEC Scientist B - Section B: 47
INCA(Increase register A by $1$) is an example of which of the following addressing mode? Immediate addressing Indirect addressing Implied addressing Relative addressing

Lakshman Patel RJIT asked in CO and Architecture Mar 30, 2020

by Lakshman Patel RJIT

1.6k views

1 vote

2 answers

7

NIELIT 2017 DEC Scientist B - Section B: 59
A two-word instruction is stored in a location $A$. The operand part of instruction holds $B$. If the addressing mode is relative, the operand is available in location $A+B+2$ $A+B+1$ $B+1$ $A+B$

Lakshman Patel RJIT asked in CO and Architecture Mar 30, 2020

by Lakshman Patel RJIT

850 views

0 votes

2 answers

8

UGCNET-Jan2017-III: 4
Match the following : ... $\text{a-iv, b-ii, c-i, d-iii}$ $\text{a-iv, b-iii, c-ii, d-i}$

go_editor asked in CO and Architecture Mar 24, 2020

552 views

3 votes

5 answers

9

ISRO2020-15
A stack organized computer is characterised by instructions with indirect addressing direct addressing zero addressing index addressing

Satbir asked in CO and Architecture Jan 13, 2020

by Satbir

2.4k views

2 votes

3 answers

10

ISRO2020-1
The immediate addressing mode can be used for Loading internal registers with initial values Perform arithmetic or logical operation on data contained in instructions Which of the following is true? Only $1$ Only $2$ Both $1$ and $2$ Immediate mode refers to data in cache

Satbir asked in CO and Architecture Jan 13, 2020

by Satbir

1.3k views

7 votes

2 answers

11

ISRO2020-8
Consider a $32$- bit processor which supports $70$ instructions. Each instruction is $32$ bit long and has $4$ fields namely opcode, two register identifiers and an immediate operand of unsigned integer type. Maximum value of the immediate operand that can be supported by the processor is $8191$. How many registers the processor has? $32$ $64$ $128$ $16$

Satbir asked in CO and Architecture Jan 13, 2020

by Satbir

2.0k views

4 votes

3 answers

12

UGCNET-June-2019-II: 11
Which type of addressing mode, less number of memory references are required? Immediate Implied Register Indexed

Arjun asked in CO and Architecture Jul 2, 2019

by Arjun

4.5k views

0 votes

2 answers

13

machine instructions and addressing modes
A digital computer has memory unit with $24$ bits word.The instruction set consists of $150$ different operations. All instructions have an operation code part and an address part. Each instruction is stored in one word of memory. $Q1$ How many bits are needed for the OP-CODE and ... $2^{16}, 2^{24}$ $2^{16},2^{24}-1$ $\textrm{None of these}$

Gitika Babbar asked in CO and Architecture May 24, 2019

by Gitika Babbar

1.2k views

0 votes

1 answer

14

Self doubt
Can anyone please explain in simple terms indexed, relative and base register addressing modes?

subho16 asked in CO and Architecture Jan 19, 2019

268 views

1 vote

1 answer

15

What is mean by "Index Value" in Indexed Addressing Mode?
If someone mentioned "index value" in indexed addressing mode then which value is it referring; the value of index register or the constant value? It should be value of index register, isn't it? But from the given snippet it seems that they are referring constant value Please clarify Thank You

newbie asked in CO and Architecture Jan 8, 2019

by newbie

643 views

0 votes

1 answer

16

UPPCL AE 2018:45
In which of the following cases, a process executing in user mode requires an entry into the $\text{OS}$ mode? Decrementing an unsigned integer value stored in a register beyond zero Adding values of two registers using $\textsf{ADD}$ instruction Executing $\textsf{printf} ()$ Accessing a general purpose register

Lakshman Patel RJIT asked in CO and Architecture Jan 5, 2019

by Lakshman Patel RJIT

117 views

1 vote

1 answer

17

Indirect index addressing mode
I know about indirect addressing mode , Index addressing mode but do not know about Indirect index addressing mode ? in one solution of a question they told that Indirect index addressing mode does not add some constant value (base address etc ) while calculating the effective address i did not found it on google etc explain Indirect index addressing mode

Gurdeep Saini asked in CO and Architecture Jan 4, 2019

by Gurdeep Saini

609 views

0 votes

3 answers

18

MadeEasy Test Series: CO & Architecture - Addressing Modes
The Data transfer instruction size is $64-bit$ ALU, ALU operation instruction size is $32-bit$ and branch instruction size is $16-bit$. Assume program has been loaded in the memory starting from address 3000 decimal. If an ... executing, PC value will be 3030, but given answer is 3028 Previous Q: https://gateoverflow.in/1058/gate2004-63

Learner_jai asked in CO and Architecture Dec 27, 2018

1.1k views

0 votes

1 answer

19

NTA NET DEC 2018 Q44

Sanjay Sharma asked in CO and Architecture Dec 25, 2018

by Sanjay Sharma

340 views

1 vote

1 answer

20

Testbook Test Series: CO & Architecture - Addressing Modes
A PC-related mode branch instruction is $8$Byte long. The address of the instruction,in decimal, is $548321.$Find the branch target address if the signed displacement in the instruction is $-29?$

Lakshman Patel RJIT asked in CO and Architecture Dec 23, 2018

by Lakshman Patel RJIT

484 views

1 vote

3 answers

21

NIELIT 2018-82
Identify the true statement from the given statements. Program relocation at run time requires transfer complete block to some memory locations requires both base address and relative address requires only absolute address $1$ $1$ and $2$ $1$ , $2$ and $3$ $1$ and $3$

Arjun asked in CO and Architecture Dec 7, 2018

by Arjun

1.3k views

0 votes

2 answers

22

Memory Access-self doubt
what is the number of memory accessed required in register indirect mode index register mode base register mode pls explain in details with examples

aditi19 asked in CO and Architecture Nov 30, 2018

330 views

5 votes

1 answer

23

Addressing Mode
Consider we have an instruction Load 1000. Given Memory and Register R1 as Follows. What is the actual value Loaded in the accumulator ? A. 1000 1400 1300 1000 B. 1400 1300 1000 1000 C. 1000 1300 1400 1000 D. 1300 1000 1400 1000

Na462 asked in CO and Architecture Oct 12, 2018

by Na462

1.7k views

1 vote

0 answers

24

self doubt
How stack addressing is related to Reentranecy ,can anyone explain it?

Prince Sindhiya asked in CO and Architecture Sep 27, 2018

by Prince Sindhiya

186 views

0 votes

0 answers

25

Self Doubt on GATE2005-65
https://gateoverflow.in/1388/gate2005-65 $\text{In this question, what will be the number of }$ $\textbf{cycles}$ $\text{needed during execution cycle of instruction}$ $\text{According to me I am getting 6 cycles. Please tell what could be the correct answer for it}$

!KARAN asked in CO and Architecture Sep 10, 2018

by !KARAN

480 views

0 votes

1 answer

26

Addressing Instructions
Are memory to memory instructions allowed? Eg. ADD [123], [345] or MOV [123], [343] If not, then why?

Asutosh asked in CO and Architecture Sep 6, 2018

318 views

7 votes

0 answers

27

Addressing Mode
Addressing Mode. Instruction Meaning Description $1.$Register Addressing Mode (or) Register Direct AM $\text{Add} R_{1},R_{2}$ $R_{1}\leftarrow R_{1}+R_{2}$ ... ? Plz check https://www.slideshare.net/aliasgharmanjotho11/addressing-modes-37108170 http://web.cs.iastate.edu/~prabhu/Tutorial/PIPELINE/addressMode.html

srestha asked in CO and Architecture Aug 28, 2018

1.4k views

2 votes

0 answers

28

Addressing modes
Instructions are stored in memory. When they are to be executed they are brought into instruction register. Now it is divided as Mode, opcode, operand (log (memory size) is divided in three parts) . In direct addressing, operand represent the effective ... required to address a memory then how such a big instruction is stored in memory whose operand itself has those many bits?

tusharp asked in CO and Architecture Aug 15, 2018

441 views

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