Recent questions tagged addressing-modes

+2 votes

1 answer

1

UGCNET-June-2019-II-11
Which type of addressing mode, less number of memory references are required? Immediate Implied Register Indexed

asked Jul 2 in CO and Architecture by Arjun Veteran (416k points) | 92 views

0 votes

2 answers

2

machine instructions and addressing modes
A digital computer has memory unit with $24$ bits word.The instruction set consists of $150$ different operations. All instructions have an operation code part and an address part. Each instruction is stored in one word of memory. $Q1$ How many bits are needed for the OP-CODE and ... $2^{16}, 2^{24}$ $2^{16},2^{24}-1$ $\textrm{None of these}$

asked May 24 in CO and Architecture by Gitika Babbar (147 points) | 72 views

0 votes

1 answer

3

Self doubt
Can anyone please explain in simple terms indexed, relative and base register addressing modes?

asked Jan 19 in CO and Architecture by subho16 (135 points) | 68 views

0 votes

1 answer

4

What is mean by "Index Value" in Indexed Addressing Mode?
If someone mentioned "index value" in indexed addressing mode then which value is it referring; the value of index register or the constant value? It should be value of index register, isn't it? But from the given snippet it seems that they are referring constant value Please clarify Thank You

asked Jan 8 in CO and Architecture by newbie (57 points) | 106 views

0 votes

0 answers

5

Indirect index addressing mode
I know about indirect addressing mode , Index addressing mode but do not know about Indirect index addressing mode ? in one solution of a question they told that Indirect index addressing mode does not add some constant value (base address etc ) while calculating the effective address i did not found it on google etc explain Indirect index addressing mode

asked Jan 4 in CO and Architecture by Gurdeep Saini Loyal (9.9k points) | 72 views

0 votes

0 answers

6

MadeEasy Test Series: CO & Architecture - Addressing Modes
The Data transfer instruction size is $64-bit$ ALU, ALU operation instruction size is $32-bit$ and branch instruction size is $16-bit$. Assume program has been loaded in the memory starting from address 3000 decimal. If an ... executing, PC value will be 3030, but given answer is 3028 Previous Q: https://gateoverflow.in/1058/gate2004-63

asked Dec 27, 2018 in CO and Architecture by Learner_jai Active (2.6k points) | 138 views

0 votes

1 answer

7

NTA NET DEC 2018 Q44

asked Dec 25, 2018 in CO and Architecture by Sanjay Sharma Boss (48.2k points) | 104 views

0 votes

1 answer

8

Testbook Test Series: CO & Architecture - Addressing Modes
A PC-related mode branch instruction is $8$Byte long. The address of the instruction,in decimal, is $548321.$Find the branch target address if the signed displacement in the instruction is $-29?$

asked Dec 23, 2018 in CO and Architecture by Lakshman Patel RJIT Boss (45.8k points) | 111 views

0 votes

2 answers

9

Memory Access-self doubt
what is the number of memory accessed required in register indirect mode index register mode base register mode pls explain in details with examples

asked Nov 30, 2018 in CO and Architecture by aditi19 Active (4k points) | 73 views

+2 votes

1 answer

10

Addressing Mode
Consider we have an instruction Load 1000. Given Memory and Register R1 as Follows. What is the actual value Loaded in the accumulator ? A. 1000 1400 1300 1000 B. 1400 1300 1000 1000 C. 1000 1300 1400 1000 D. 1300 1000 1400 1000

asked Oct 12, 2018 in CO and Architecture by Na462 Loyal (6.7k points) | 186 views

+1 vote

1 answer

11

TESTBOOK TEST SERIES
A register to register machine supports 2-address. 1-address and zero-address instructions instruction register size is 24 bits and register set size is 480. If there are 48 2-address instructions and 2048 Zero - address instructions then what is the maximum possible number of 1 - address instruction?

asked Sep 30, 2018 in CO and Architecture by Avik Chowdhury Junior (621 points) | 151 views

+1 vote

0 answers

12

self doubt
How stack addressing is related to Reentranecy ,can anyone explain it?

asked Sep 27, 2018 in CO and Architecture by Prince Sindhiya Loyal (5.4k points) | 46 views

0 votes

0 answers

13

Self Doubt on GATE2005-65
https://gateoverflow.in/1388/gate2005-65 $\text{In this question, what will be the number of }$ $\textbf{cycles}$ $\text{needed during execution cycle of instruction}$ $\text{According to me I am getting 6 cycles. Please tell what could be the correct answer for it}$

asked Sep 10, 2018 in CO and Architecture by !KARAN Active (1.9k points) | 115 views

0 votes

0 answers

14

Addressing Instructions
Are memory to memory instructions allowed? Eg. ADD [123], [345] or MOV [123], [343] If not, then why?

asked Sep 6, 2018 in CO and Architecture by Asutosh (477 points) | 78 views

+5 votes

0 answers

15

Addressing Mode
Addressing Mode. Instruction Meaning Description $1.$Register Addressing Mode (or) Register Direct AM $\text{Add} R_{1},R_{2}$ $R_{1}\leftarrow R_{1}+R_{2}$ ... ? Plz check https://www.slideshare.net/aliasgharmanjotho11/addressing-modes-37108170 http://web.cs.iastate.edu/~prabhu/Tutorial/PIPELINE/addressMode.html

asked Aug 28, 2018 in CO and Architecture by srestha Veteran (113k points) | 236 views

+1 vote

0 answers

16

Addressing modes
Instructions are stored in memory. When they are to be executed they are brought into instruction register. Now it is divided as Mode, opcode, operand (log (memory size) is divided in three parts) . In direct addressing, operand represent the effective ... required to address a memory then how such a big instruction is stored in memory whose operand itself has those many bits?

asked Aug 15, 2018 in CO and Architecture by tusharp Loyal (6.7k points) | 146 views

+3 votes

1 answer

17

Instruction Addressing
A computer has 170 different operations. Word size is 4 bytes one word instructions requires two address fields. One address for register and one address for memory. If there are 37 registers then the memory size is ______________(in KB). Ans. 256KB

asked Jul 31, 2018 in CO and Architecture by Na462 Loyal (6.7k points) | 296 views

+1 vote

1 answer

18

Addressing mode

asked May 27, 2018 in CO and Architecture by Prateek Raghuvanshi Boss (10.3k points) | 179 views

+1 vote

2 answers

19

Ace Test Series 2019: CO & Architecture - Number Of Zero Address Instructions
A system has 16 bits instruction that support zero address, one address and two address instructions Assume each address field size is 5 bits it is designed for supporting 40' number of two address ... ' number of one address instructions. The maximum number of zero address instructions that can be formulated is

asked May 11, 2018 in CO and Architecture by Kartavya Kothari (107 points) | 130 views

+1 vote

2 answers

20

addressing modes

asked May 10, 2018 in CO and Architecture by Sanjay Sharma Boss (48.2k points) | 188 views

+1 vote

1 answer

21

Addressing mode
Plz describe Which addressing mode does this following line represents and how? Index addressing mode, $X\left ( R_{1} \right )$, where $X$ is an offset represented in $2$'s complement $16$ bit representation

asked Apr 26, 2018 in CO and Architecture by srestha Veteran (113k points) | 183 views

+2 votes

1 answer

22

Addressing Mode
Adding a constant to the content of register Is it a)Immediate mode or b) Indexed mode?

asked Apr 15, 2018 in CO and Architecture by srestha Veteran (113k points) | 334 views

+1 vote

0 answers

23

MadeEasy Test Series: CO & Architecture - Addressing Modes
A computer has 256 KB, 8 way set associative write back data cache with block size 16 bytes. The processor send 36 bit addresses to the cache controller. Each tag directory entry contains, in addition to tag address, 1 valid bit and 1 matching bit. The size of ... above till here: TAG Size = $23\ bits * 2^{14}$ = $3\ bytes * 2^{14}$ = 48 KB

asked Jan 30, 2018 in CO and Architecture by Rishabh Gupta 2 Boss (17k points) | 220 views

+4 votes

1 answer

24

CO Addressing
A computer has 32 bit instruction and 12 bit address . If there are 250 two address instructions , the no. of one -address instructions can be ..... Plz formulate a generic solution for this with diagram .

asked Jan 25, 2018 in CO and Architecture by ashwina Active (1.7k points) | 268 views

+5 votes

1 answer

25

Addresing mode
Please Explain in detail

asked Jan 16, 2018 in CO and Architecture by Shubham Kumar Gupta (443 points) | 161 views

+4 votes

0 answers

26

CO: Addressing Mode Question

asked Jan 11, 2018 in CO and Architecture by thepeeyoosh Active (1.9k points) | 607 views

+1 vote

1 answer

27

Effective Address Calculation
Plz discuss every part with detailed solution with diagram .

asked Jan 2, 2018 in CO and Architecture by ashwina Active (1.7k points) | 1.1k views

+3 votes

1 answer

28

Addressing Modes
How many memory accesses required by the following instructions? SUB r1, r2, r3 MUL r1, r2, (r3) DIV r1, r2, @(r4) Suppose every instruction is one word long, as well as every address. (A) 4 (B) 6 (C) 8 (D) 9

asked Dec 20, 2017 in CO and Architecture by ankitgupta.1729 Boss (14k points) | 314 views

+3 votes

0 answers

29

Relative Addressing Mode
A two- word instruction is stored in a location A. The operand part of instruction holds B. If the addressing mode is relative , the operand is available in location : A. A+B+2 B.A+B+1 C.B+1 D.A+B Explain with diagram.

asked Dec 17, 2017 in CO and Architecture by ashwina Active (1.7k points) | 634 views

+3 votes

2 answers

30

ISRO-DEC2017-43
Consider an instruction of the type $\text{LW R1, 20(R2)}$ which during execution reads a $32$-$bit$ word from memory and stores it in a $32$-$bit$ register $R1.$ The effective address of the memory location is obtained ... $20$ and contents of $R2.$ Which one best reflects the source operand? Immediate addressing Register addressing Register Indirect addressing Indexed addressing

asked Dec 17, 2017 in CO and Architecture by gatecse Boss (16.1k points) | 599 views

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