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Recent questions tagged addressing-modes
2
votes
2
answers
151
UGC NET CSE | June 2014 | Part 3 | Question: 40
The advantage of _______ is that it can reference memory without paying the price of having a full memory address in the instruction. Direct addressing Indexed addressing Register addressing Register Indirect addressing
The advantage of _______ is that it can reference memory without paying the price of having a full memory address in the instruction. Direct addressingIndexed addressingR...
makhdoom ghaya
2.1k
views
makhdoom ghaya
asked
Jul 10, 2016
CO and Architecture
ugcnetjune2014iii
co-and-architecture
addressing-modes
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1
votes
1
answer
152
UGC NET CSE | June 2012 | Part 3 | Question: 27
Identify the addressing modes of the below instructions and match them : ... $\text{a-iii, b-ii, c-i, d-iv}$ $\text{a-iv, b-iii, c-ii, d-i}$
Identify the addressing modes of the below instructions and match them :$\begin{array}{} \text{(a)} & \text{ADI} & \text{(i)} & \text{Immediate addressing} \\ \text{(b)}...
go_editor
2.0k
views
go_editor
asked
Jul 7, 2016
CO and Architecture
ugcnetcse-june2012-paper3
co-and-architecture
addressing-modes
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2
votes
4
answers
153
immediate Addressing
himanich
1.9k
views
himanich
asked
Jun 29, 2016
CO and Architecture
co-and-architecture
addressing-modes
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0
votes
1
answer
154
Calculate effective memory address
A two word instruction.is stored at location W. Address field of the instruction ( stored at W+1) holds value Y. If program counter value is PC, What is the effective address of this instruction?
A two word instruction.is stored at location W. Address field of the instruction ( stored at W+1) holds value Y. If program counter value is PC, What is the effective add...
sh!va
1.7k
views
sh!va
asked
Jun 16, 2016
CO and Architecture
addressing-modes
co-and-architecture
+
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7
votes
4
answers
155
ISRO2009-21, UGCNET-Dec2012-II: 12
In which addressing mode, the effectives address of the operand is generated by adding a constant value to the content of a register? Absolute mode Indirect mode Immediate mode Index mode
In which addressing mode, the effectives address of the operand is generated by adding a constant value to the content of a register?Absolute modeIndirect modeImmediate m...
Desert_Warrior
6.1k
views
Desert_Warrior
asked
Jun 3, 2016
CO and Architecture
isro2009
co-and-architecture
ugcnetcse-dec2012-paper2
addressing-modes
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2
votes
1
answer
156
CO: Addressing Modes
Consider 1GHz clock frequency processor, uses different operand access modes shown below: Assume that 8 cycle consumed for memory reference, 4 cycles consumed for arithmetic computation and 0 cycles consumed when the operand is in register instruction itself. What is the average ... the processor? 117.45 M words/sec 113.63 M words/sec 217.45 M words/sec 316.45 M words/sec
Consider 1GHz clock frequency processor, uses different operand access modes shown below: Assume that 8 cycle consumed for memory reference, 4 cycles consumed for a...
Prasanna
1.1k
views
Prasanna
asked
Jan 6, 2016
CO and Architecture
addressing-modes
co-and-architecture
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1
votes
3
answers
157
Ace Test Series: CO & Architecture - Addressing Modes
Given answer is A. I am doubtful between A and B why not B is faster than A. Please explain
Given answer is A. I am doubtful between A and B why not B is faster than A. Please explain
shikharV
1.5k
views
shikharV
asked
Jan 4, 2016
CO and Architecture
ace-test-series
co-and-architecture
addressing-modes
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2
votes
0
answers
158
MadeEasy Test Series: CO & Architecture - Addressing Modes
Q.14 Which of the following is most relevant addressing mode used to write code in which reallocation done at run time? Indexed mode Indirect mode Direct mode Relative mode Related to https://gateoverflow.in/3578/gate2006-it_39 https://gateoverflow.in/1656/gate1998_1-19
Q.14Which of the following is most relevant addressing mode used to write code in which reallocation done at run time?Indexed modeIndirect modeDirect modeRelative modeRel...
Akash Kanase
514
views
Akash Kanase
asked
Dec 19, 2015
CO and Architecture
co-and-architecture
addressing-modes
made-easy-test-series
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3
votes
3
answers
159
Addressing mode used by PC
Himanshu1
2.4k
views
Himanshu1
asked
Dec 4, 2015
CO and Architecture
co-and-architecture
addressing-modes
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6
votes
2
answers
160
memory addressing
Consider $1 \text{GHz}$ clock frequency processor,uses different operand accessing models shown below: Operand Accessing Mode Frequency(%) Register 10 Immediate 20 Direct 30 Memory Indirect 20 Indexed 20 Assume that $2$ memory cycles consumed for memory reference , ... operand fetch rate (in millions $\text{words/sec}$) of processor is __________ (upto 2 to decimal places).
Consider $1 \text{GHz}$ clock frequency processor,uses different operand accessing models shown below:Operand Accessing ModeFrequency(%)Register10Immediate20Direct30Memor...
Shefali
4.3k
views
Shefali
asked
Nov 8, 2015
CO and Architecture
addressing-modes
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2
votes
2
answers
161
which addressing modes in this question
Sourabh Kumar 1
949
views
Sourabh Kumar 1
asked
Oct 30, 2015
CO and Architecture
addressing-modes
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11
votes
2
answers
162
ISRO2011-5
$\textsf{MOV [BX], AL}$ type of data addressing is called? register immediate register indirect register relative
$\textsf{MOV [BX], AL}$ type of data addressing is called?registerimmediateregister indirectregister relative
amarVashishth
5.6k
views
amarVashishth
asked
Oct 11, 2015
CO and Architecture
isro2011
co-and-architecture
addressing-modes
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12
votes
3
answers
163
Max number of one address instruction, when two address instruction is given is?
A computer uses expanding opcode. It has 16 bit instructions 6 bit addresses, it supports one address, two address instructions only. If there are n two address instructions, the maximum number of one address instructions are?
A computer uses expanding opcode. It has 16 bit instructions 6 bit addresses, it supports one address, two address instructions only. If there are n two address instructi...
Tehreem
11.7k
views
Tehreem
asked
Sep 9, 2015
CO and Architecture
co-and-architecture
addressing-modes
machine-instruction
instruction-format
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8
votes
1
answer
164
Number of one address instruction
Assume an instruction set that uses a fixed $16-bit$ instruction length. Operand specifiers are $6 $bits in length. There are $K$ two-operand instructions and $L$ zero-operand instructions. What is the maximum number of one-operand instructions that can be supported?
Assume an instruction set that uses a fixed $16-bit$ instruction length. Operand specifiers are $6 $bits in length. There are $K$ two-operand instructions and $L$ zero-op...
focus _GATE
7.8k
views
focus _GATE
asked
Jun 3, 2015
CO and Architecture
addressing-modes
co-and-architecture
+
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40
votes
3
answers
165
GATE IT 2006 | Question: 40
The memory locations $1000,1001$ and $1020$ have data values $18,1$ and $16$ ... value $20$ Memory location $1020$ has value $20$ Memory location $1021$ has value $20$ Memory location $1001$ has value $20$
The memory locations $1000,1001$ and $1020$ have data values $18,1$ and $16$ respectively before the following program is executed.$$\begin{array}{ll} \text{MOVI} & \text...
Ishrat Jahan
17.1k
views
Ishrat Jahan
asked
Oct 31, 2014
CO and Architecture
gateit-2006
co-and-architecture
addressing-modes
normal
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56
votes
3
answers
166
GATE IT 2006 | Question: 39, ISRO2009-42
Which of the following statements about relative addressing mode is FALSE? It enables reduced instruction size It allows indexing of array element with same instruction It enables easy relocation of data It enables faster address calculation than absolute addressing
Which of the following statements about relative addressing mode is FALSE?It enables reduced instruction sizeIt allows indexing of array element with same instructionIt e...
Ishrat Jahan
14.8k
views
Ishrat Jahan
asked
Oct 31, 2014
CO and Architecture
gateit-2006
co-and-architecture
addressing-modes
normal
isro2009
+
–
35
votes
6
answers
167
GATE CSE 1996 | Question: 1.16, ISRO2016-42
Relative mode of addressing is most relevant to writing: Co – routines Position – independent code Shareable code Interrupt Handlers
Relative mode of addressing is most relevant to writing:Co – routinesPosition – independent codeShareable codeInterrupt Handlers
Kathleen
12.5k
views
Kathleen
asked
Oct 9, 2014
CO and Architecture
gate1996
co-and-architecture
addressing-modes
easy
isro2016
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31
votes
3
answers
168
GATE CSE 1993 | Question: 10
The instruction format of a CPU is: $\text{Mode}$ and $\text{RegR}$ together specify the operand. $\text{RegR}$ specifies a CPU register and $\text{Mode}$ specifies an addressing mode. In particular, $\text{Mode}=2$ specifies that ... address of the operand? Assuming that is a non-jump instruction, what are the contents of PC after the execution of this instruction?
The instruction format of a CPU is:$\text{Mode}$ and $\text{RegR}$ together specify the operand. $\text{RegR}$ specifies a CPU register and $\text{Mode}$ specifies an add...
Kathleen
7.0k
views
Kathleen
asked
Sep 29, 2014
CO and Architecture
gate1993
co-and-architecture
addressing-modes
normal
descriptive
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48
votes
5
answers
169
GATE CSE 2011 | Question: 21
Consider a hypothetical processor with an instruction of type $\text{LW R1, 20(R2)}$, which during execution reads a $32\text{-bit}$ word from memory and stores it in a $32\text{-bit}$ ... mode implemented by this instruction for the operand in memory? Immediate addressing Register addressing Register Indirect Scaled Addressing Base Indexed Addressing
Consider a hypothetical processor with an instruction of type $\text{LW R1, 20(R2)}$, which during execution reads a $32\text{-bit}$ word from memory and stores it in a ...
go_editor
17.4k
views
go_editor
asked
Sep 29, 2014
CO and Architecture
gatecse-2011
co-and-architecture
addressing-modes
easy
+
–
40
votes
4
answers
170
GATE CSE 1998 | Question: 1.19
Which of the following addressing modes permits relocation without any change whatsoever in the code? Indirect addressing Indexed addressing Base register addressing PC relative addressing
Which of the following addressing modes permits relocation without any change whatsoever in the code?Indirect addressingIndexed addressingBase register addressingPC relat...
Kathleen
10.9k
views
Kathleen
asked
Sep 25, 2014
CO and Architecture
gate1998
co-and-architecture
addressing-modes
easy
+
–
54
votes
3
answers
171
GATE CSE 1999 | Question: 2.23
A certain processor supports only the immediate and the direct addressing modes. Which of the following programming language features cannot be implemented on this processor? Pointers Arrays Records Recursive procedures with local variable
A certain processor supports only the immediate and the direct addressing modes. Which of the following programming language features cannot be implemented on this proces...
Kathleen
15.4k
views
Kathleen
asked
Sep 23, 2014
CO and Architecture
gate1999
co-and-architecture
addressing-modes
normal
multiple-selects
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7
votes
1
answer
172
Pc relative mode addressing
What is the intial pc value meaning 530=Pc + value what should be the pc value 631 or 632 or 633 basically the instruction length is not give so how can i determine the addr loaded in pc hen instructtion at 630 is executing because if instruction length is 4 bytes it should be 634 thanks in advance
What is the intial pc value meaning 530=Pc + value what should be the pc value 631 or 632 or 633 basically the instruction length is not give so how can i determine the a...
Kriss Singh
5.0k
views
Kriss Singh
asked
Sep 23, 2014
CO and Architecture
co-and-architecture
addressing-modes
+
–
27
votes
1
answer
173
GATE CSE 2005 | Question: 66
Match each of the high level language statements given on the left hand side with the most natural addressing mode from those listed on the right hand side. ... $(1, b), (2, c), (3, a)$ $(1, a), (2, b), (3, c)$
Match each of the high level language statements given on the left hand side with the most natural addressing mode from those listed on the right hand side.$$\begin{array...
Kathleen
6.8k
views
Kathleen
asked
Sep 22, 2014
CO and Architecture
gatecse-2005
co-and-architecture
addressing-modes
match-the-following
easy
+
–
97
votes
8
answers
174
GATE CSE 2005 | Question: 65
Consider a three word machine instruction $\text{ADD} A[R_0], @B$ The first operand (destination) $ A[R_0] $ uses indexed addressing mode with $R_0$ as the index register. The second operand (source) $ @B $ uses indirect addressing mode. $A$ and $B$ ... (first operand). The number of memory cycles needed during the execution cycle of the instruction is: $3$ $4$ $5$ $6$
Consider a three word machine instruction$\text{ADD} A[R_0], @B$The first operand (destination) $“A[R_0]”$ uses indexed addressing mode with $R_0$ as the index regist...
Kathleen
33.9k
views
Kathleen
asked
Sep 22, 2014
CO and Architecture
gatecse-2005
co-and-architecture
addressing-modes
normal
+
–
41
votes
4
answers
175
GATE CSE 2004 | Question: 20
Which of the following addressing modes are suitable for program relocation at run time? Absolute addressing Based addressing Relative addressing Indirect addressing I and IV I and II II and III I, II and IV
Which of the following addressing modes are suitable for program relocation at run time?Absolute addressingBased addressingRelative addressingIndirect addressingI and IVI...
Kathleen
12.0k
views
Kathleen
asked
Sep 18, 2014
CO and Architecture
gatecse-2004
co-and-architecture
addressing-modes
easy
+
–
32
votes
5
answers
176
GATE CSE 2002 | Question: 1.24
In the absolute addressing mode: the operand is inside the instruction the address of the operand in inside the instruction the register containing the address of the operand is specified inside the instruction the location of the operand is implicit
In the absolute addressing mode:the operand is inside the instructionthe address of the operand in inside the instructionthe register containing the address of the operan...
Kathleen
13.7k
views
Kathleen
asked
Sep 15, 2014
CO and Architecture
gatecse-2002
co-and-architecture
addressing-modes
easy
+
–
33
votes
2
answers
177
GATE CSE 2001 | Question: 2.9
Which is the most appropriate match for the items in the first column with the items in the second column: ... ), (Y, III), (Z, I) (X, III), (Y, II), (Z, I) (X, I), (Y, III), (Z, II)
Which is the most appropriate match for the items in the first column with the items in the second column:$$\begin{array}{|cl|cl|} \hline \text{X.} &\text{Indirect Addres...
Kathleen
7.4k
views
Kathleen
asked
Sep 14, 2014
CO and Architecture
gatecse-2001
co-and-architecture
addressing-modes
easy
match-the-following
+
–
28
votes
2
answers
178
GATE CSE 2000 | Question: 1.10
The most appropriate matching for the following pairs$\begin{array}{ll} \text{X: Indirect addressing} & \text{1: Loops } \\ \text{Y: Immediate addressing } & \text{2: Pointers} \\ \text{Z: Auto decrement addressing } & \text{3: Constants } \\ \end{array}$ is $X - 3, Y - 2, Z - 1$ $X - 1, Y - 3, Z - 2$ $X - 2, Y - 3, Z - 1$ $X - 3, Y - 1, Z - 2$
The most appropriate matching for the following pairs$$\begin{array}{ll} \text{X: Indirect addressing} & \text{1: Loops } \\ \text{Y: Immediate addressing } & \text{2: P...
Kathleen
8.4k
views
Kathleen
asked
Sep 14, 2014
CO and Architecture
gatecse-2000
co-and-architecture
easy
addressing-modes
match-the-following
+
–
58
votes
4
answers
179
GATE CSE 2008 | Question: 33, ISRO2009-80
Which of the following is/are true of the auto-increment addressing mode? It is useful in creating self-relocating code If it is included in an Instruction Set Architecture, then an additional ALU is required for effective address calculation The amount of increment depends on the size of the data item accessed I only II only III only II and III only
Which of the following is/are true of the auto-increment addressing mode?It is useful in creating self-relocating codeIf it is included in an Instruction Set Architecture...
Kathleen
18.4k
views
Kathleen
asked
Sep 12, 2014
CO and Architecture
gatecse-2008
addressing-modes
co-and-architecture
normal
isro2009
+
–
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