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Recent questions tagged addressing-modes
0
votes
2
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61
TestBook- Addressing Modes
A register to register machine supports 2–address, 1-address and zero–address instructions. Instruction register size is 24 bits and register set size is 480. If there are 48 2–address instructions and 2048 zero – address instructions then what is the maximum possible number of 1 – address instruction?
A register to register machine supports 2–address, 1-address and zero–address instructions. Instruction register size is 24 bits and register set size is 480.If there...
anjali007
490
views
anjali007
asked
Dec 4, 2018
CO and Architecture
co-and-architecture
addressing-modes
testbook-test-series
numerical-answers
+
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0
votes
0
answers
62
testbook
Consider a hypothetical processor with an instruction of type LDR R1, [R2, #4], in which during execution the load value at the memory location is pointed to by the effective address. The effective address of the memory location is obtained by the ... in memory? 1 Post-indexing 2 auto-indexing 3 Pre-indexed addressing with auto-indexing 4 Post-indexed addressing with auto-indexing
Consider a hypothetical processor with an instruction of type LDR R1, [R2, #4], in which during execution the load value at the memory location is pointed to by the effec...
priyanka manwani
292
views
priyanka manwani
asked
Dec 2, 2018
CO and Architecture
co-and-architecture
addressing-modes
testbook-test-series
+
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1
votes
1
answer
63
Branch Instruction
Assume that the base register contains 32856. The program counter is currently having a value of 25687 memory location. What is the branch address if the address field of jump instruction contains -30 in the address field and instruction is designed with base register addressing mode? 32826 25657 32886 25717
Assume that the base register contains 32856. The program counter is currently having a value of 25687 memory location. What is the branch address if the address field of...
Na462
507
views
Na462
asked
Dec 2, 2018
CO and Architecture
co-and-architecture
branch-conditional-instructions
addressing-modes
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0
votes
2
answers
64
Memory Access-self doubt
what is the number of memory accessed required in register indirect mode index register mode base register mode pls explain in details with examples
what is the number of memory accessed required inregister indirect modeindex register modebase register modepls explain in details with examples
aditi19
551
views
aditi19
asked
Nov 30, 2018
CO and Architecture
co-and-architecture
addressing-modes
effective-memory-access
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–
0
votes
0
answers
65
adressing modes
For Given machine instructions LW R4 #400 L1:LW R1, 0,(R4) LW R2 400(R4) ADDI R3, R1, R2 SW R3, 0(R4) SUB R4, R4, #4 BNZ R4, L1 on a 5 stage pipeline processor, 1 clock cycle per stage. how mAny clock cycles willtake execution of this segment on the regular architecture?
For Given machine instructionsLW R4 #400L1:LW R1, 0,(R4)LW R2 400(R4)ADDI R3, R1, R2SW R3, 0(R4)SUB R4, R4, #4BNZ R4, L1on a 5 stage pipeline processor, 1 clock cycle per...
rishabhdevsingh1
634
views
rishabhdevsingh1
asked
Nov 10, 2018
CO and Architecture
co-and-architecture
machine-instruction
registers
pipelining
addressing-modes
numerical-answers
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–
0
votes
1
answer
66
adressing modes
Given 2 machine instructions, LW R4 #400 LW R1, 0,(R4) IN second instruction what will be loaded in R1,is it the operand at memory location 400?or some random memory location operand..I want to clarify whether the value stored in register is same as adress that register points.
Given 2 machine instructions,LW R4 #400LW R1, 0,(R4)IN second instruction what will be loaded in R1,is it the operand at memory location 400?or some random memory locatio...
rishabhdevsingh1
1.2k
views
rishabhdevsingh1
asked
Nov 9, 2018
CO and Architecture
co-and-architecture
machine-instruction
addressing-modes
registers
numerical-answers
+
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0
votes
1
answer
67
ACE TEST SERIES QUESTION
Shankar Kakde
243
views
Shankar Kakde
asked
Nov 2, 2018
CO and Architecture
co-and-architecture
addressing-modes
numerical-answers
ace-test-series
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–
0
votes
1
answer
68
Test Series
A two-word instruction "JMP 65" is located from the address 200010. What is the effective address computed if the instruction follows relative addressing mode? My answer is 2065, Why should it be 2067
A two-word instruction "JMP 65" is located from the address 200010. What is the effective address computed if the instruction follows relative addressing mode? My answer ...
Gupta731
337
views
Gupta731
asked
Oct 31, 2018
CO and Architecture
co-and-architecture
addressing-modes
test-series
numerical-answers
+
–
0
votes
1
answer
69
Effective address
Choose the correct formula for Effective Address calculation Base + (Size*Scale) +Displacement) (Base + Size)*Scale +Displacement Base + Size*(Scale +Displacement) (Base + Size)*(Scale +Displacement)
Choose the correct formula for Effective Address calculationBase + (Size*Scale) +Displacement)(Base + Size)*Scale +DisplacementBase + Size*(Scale +Displacement)(Base + Si...
Balaji Jegan
995
views
Balaji Jegan
asked
Oct 16, 2018
CO and Architecture
co-and-architecture
addressing-modes
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–
0
votes
1
answer
70
SELF DOUBT REGISTER REFERENCE
MOV R1 #23 HOW MANY REGISTER REFERENCES ARE REQUIRED?
MOV R1 #23 HOW MANY REGISTER REFERENCES ARE REQUIRED?
eyeamgj
339
views
eyeamgj
asked
Oct 12, 2018
CO and Architecture
co-and-architecture
addressing-modes
self-doubt
+
–
5
votes
1
answer
71
Addressing Mode
Consider we have an instruction Load 1000. Given Memory and Register R1 as Follows. What is the actual value Loaded in the accumulator ? A. 1000 1400 1300 1000 B. 1400 1300 1000 1000 C. 1000 1300 1400 1000 D. 1300 1000 1400 1000
Consider we have an instruction Load 1000. Given Memory and Register R1 as Follows.What is the actual value Loaded in the accumulator ?A. 1000 1400 1300 1000B. 1400 1300...
Na462
4.0k
views
Na462
asked
Oct 12, 2018
CO and Architecture
addressing-modes
co-and-architecture
made-easy-test-series
+
–
0
votes
1
answer
72
Addressing modes + pipelining
I got Option D , and Are we saving 1 cycle by replacement ? ( if yes then may be solved it correct else i am wrong somewhere )
I got Option D , and Are we saving 1 cycle by replacement ? ( if yes then may be solved it correct else i am wrong somewhere )
HeadShot
361
views
HeadShot
asked
Oct 4, 2018
CO and Architecture
co-and-architecture
addressing-modes
pipelining
+
–
1
votes
0
answers
73
self doubt
How stack addressing is related to Reentranecy ,can anyone explain it?
How stack addressing is related to Reentranecy ,can anyone explain it?
Prince Sindhiya
320
views
Prince Sindhiya
asked
Sep 27, 2018
CO and Architecture
co-and-architecture
addressing-modes
self-doubt
+
–
0
votes
1
answer
74
APDCL 2017
Hriday Das 1
205
views
Hriday Das 1
asked
Sep 24, 2018
CO and Architecture
co-and-architecture
addressing-modes
branch-unconditional-instructions
apdcl2017
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–
0
votes
1
answer
75
Branch Offset
Consider a processor where each instruction size is exactly two bytes long. Conditional and unconditional branch instructions use PC relative addressing mode with offset specified in Bytes to the target location of the branch instruction; the offset is always with ... sequence. The below program is executed (All values are specified in decimal), type of memory is byte addressable
Consider a processor where each instruction size is exactly two bytes long. Conditional and unconditional branch instructions use PC relative addressing mode with offset ...
Na462
1.1k
views
Na462
asked
Sep 24, 2018
CO and Architecture
co-and-architecture
branch-conditional-instructions
addressing-modes
numerical-answers
+
–
0
votes
1
answer
76
Self Doubt
how we generally write addressing mode in instruction. eg. immediate addressing mode: add #5 1. Direct 2. Indirect 3. Register 4. Register Indirect 5. Indexed 6. Based 7. Displacement 8. Stack
how we generally write addressing mode in instruction. eg. immediate addressing mode: add #51. Direct2. Indirect3. Register4. Register Indirect5. Indexed6. Based7. Displa...
iamdeepakji
248
views
iamdeepakji
asked
Sep 19, 2018
CO and Architecture
co-and-architecture
addressing-modes
self-doubt
+
–
0
votes
0
answers
77
Self Doubt on GATE2005-65
https://gateoverflow.in/1388/gate2005-65 $\text{In this question, what will be the number of }$ $\textbf{cycles}$ $\text{needed during execution cycle of instruction}$ $\text{According to me I am getting 6 cycles. Please tell what could be the correct answer for it}$
https://gateoverflow.in/1388/gate2005-65$\text{In this question, what will be the number of }$ $\textbf{cycles}$ $\text{needed during execution cycle of instruction}$$\te...
!KARAN
617
views
!KARAN
asked
Sep 9, 2018
CO and Architecture
usergate2005
usermod
co-and-architecture
addressing-modes
self-doubt
+
–
0
votes
1
answer
78
Instructions
Deepalitrapti
685
views
Deepalitrapti
asked
Sep 7, 2018
CO and Architecture
co-and-architecture
addressing-modes
opcode
made-easy-booklet
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–
0
votes
0
answers
79
Addressing mode
Deepalitrapti
321
views
Deepalitrapti
asked
Sep 7, 2018
CO and Architecture
co-and-architecture
addressing-modes
self-doubt
+
–
0
votes
1
answer
80
Addressing Instructions
Are memory to memory instructions allowed? Eg. ADD [123], [345] or MOV [123], [343] If not, then why?
Are memory to memory instructions allowed?Eg. ADD [123], [345] or MOV [123], [343]If not, then why?
Asutosh
490
views
Asutosh
asked
Sep 6, 2018
CO and Architecture
co-and-architecture
addressing-modes
+
–
7
votes
0
answers
81
Addressing Mode
Addressing Mode. Instruction Meaning Description $1.$Register Addressing Mode (or) Register Direct AM $\text{Add} R_{1},R_{2}$ $R_{1}\leftarrow R_{1}+R_{2}$ ... ? Plz check https://www.slideshare.net/aliasgharmanjotho11/addressing-modes-37108170 http://web.cs.iastate.edu/~prabhu/Tutorial/PIPELINE/addressMode.html
Addressing Mode. InstructionMeaningDescription$1.$Register Addressing Mode(or)Register Direct AM$\text{Add} R_{1},R_{2}$$R_{1}\leftarrow R_{1}+R_{2}$Two General...
srestha
2.1k
views
srestha
asked
Aug 28, 2018
CO and Architecture
addressing-modes
co-and-architecture
+
–
2
votes
0
answers
82
Addressing modes
Instructions are stored in memory. When they are to be executed they are brought into instruction register. Now it is divided as Mode, opcode, operand (log (memory size) is divided in three parts) . In direct addressing, operand represent the effective ... required to address a memory then how such a big instruction is stored in memory whose operand itself has those many bits?
Instructions are stored in memory. When they are to be executed they are brought into instruction register. Now it is divided as Mode, opcode, operand (log (memory size) ...
tusharp
615
views
tusharp
asked
Aug 15, 2018
CO and Architecture
addressing-modes
co-and-architecture
+
–
4
votes
2
answers
83
Instruction Addressing
A computer has 170 different operations. Word size is 4 bytes one word instructions requires two address fields. One address for register and one address for memory. If there are 37 registers then the memory size is ______________(in KB). Ans. 256KB
A computer has 170 different operations. Word size is 4 bytes one word instructions requires two address fields. One address for register and one address for memory. If t...
Na462
2.2k
views
Na462
asked
Jul 31, 2018
CO and Architecture
co-and-architecture
addressing-modes
machine-instruction
+
–
1
votes
1
answer
84
Addressing mode
Prateek Raghuvanshi
1.1k
views
Prateek Raghuvanshi
asked
May 27, 2018
CO and Architecture
addressing-modes
clock-cycles
+
–
2
votes
2
answers
85
addressing modes
Sanjay Sharma
1.1k
views
Sanjay Sharma
asked
May 10, 2018
CO and Architecture
co-and-architecture
addressing-modes
+
–
1
votes
1
answer
86
Addressing mode
Plz describe Which addressing mode does this following line represents and how? Index addressing mode, $X\left ( R_{1} \right )$, where $X$ is an offset represented in $2$'s complement $16$ bit representation
Plz describeWhich addressing mode does this following line represents and how?Index addressing mode, $X\left ( R_{1} \right )$, where $X$ is an offset represented in $2$'...
srestha
829
views
srestha
asked
Apr 26, 2018
CO and Architecture
addressing-modes
co-and-architecture
+
–
2
votes
1
answer
87
Addressing Mode
Adding a constant to the content of register Is it a)Immediate mode or b) Indexed mode?
Adding a constant to the content of registerIs ita)Immediate mode or b) Indexed mode?
srestha
1.3k
views
srestha
asked
Apr 15, 2018
CO and Architecture
addressing-modes
co-and-architecture
+
–
1
votes
0
answers
88
MadeEasy Test Series: CO & Architecture - Addressing Modes
A computer has 256 KB, 8 way set associative write back data cache with block size 16 bytes. The processor send 36 bit addresses to the cache controller. Each tag directory entry contains, in addition to tag address, 1 valid bit and 1 matching bit. The size of ... above till here: TAG Size = $23\ bits * 2^{14}$ = $3\ bytes * 2^{14}$ = 48 KB
A computer has 256 KB, 8 way set associative write back data cache with block size 16 bytes. The processor send 36 bit addresses to the cache controller. Each tag directo...
Rishabh Gupta 2
979
views
Rishabh Gupta 2
asked
Jan 30, 2018
CO and Architecture
made-easy-test-series
cache-memory
co-and-architecture
addressing-modes
+
–
4
votes
2
answers
89
CO Addressing
A computer has 32 bit instruction and 12 bit address . If there are 250 two address instructions , the no. of one -address instructions can be ..... Plz formulate a generic solution for this with diagram .
A computer has 32 bit instruction and 12 bit address . If there are 250 two address instructions , the no. of one -address instructions can be .....Plz formulate a generi...
dragonball
5.2k
views
dragonball
asked
Jan 25, 2018
CO and Architecture
co-and-architecture
addressing-modes
+
–
5
votes
1
answer
90
Addresing mode
Please Explain in detail
Please Explain in detail
Shubham Kumar Gupta
644
views
Shubham Kumar Gupta
asked
Jan 16, 2018
CO and Architecture
addressing-modes
co-and-architecture
instruction-format
+
–
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