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Recent questions tagged addressing-modes

3 votes
1 answer
92
Effective Address Calculation
Plz discuss every part with detailed solution with diagram .
Plz discuss every part with detailed solution with diagram .
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3 votes
1 answer
93
Addressing Modes
How many memory accesses required by the following instructions? SUB r1, r2, r3 MUL r1, r2, (r3) DIV r1, r2, @(r4) Suppose every instruction is one word long, as well as every address. (A) 4 (B) 6 (C) 8 (D) 9
How many memory accesses required by the following instructions?SUB r1, r2, r3MUL r1, r2, (r3)DIV r1, r2, @(r4)Suppose every instruction is one word long, as well as ever...
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6 votes
1 answer
94
Relative Addressing Mode
A two- word instruction is stored in a location A. The operand part of instruction holds B. If the addressing mode is relative , the operand is available in location : A. A+B+2 B.A+B+1 C.B+1 D.A+B Explain with diagram.
A two- word instruction is stored in a location A. The operand part of instruction holds B. If the addressing mode is relative , the operand is available in location :A. ...
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5 votes
2 answers
96
Addressing Mode
"The Address Part of the Index Addressing mode Instruction must set to zero,to behave like Register Indirect Mode Instruction" IS IT A VALID STATEMENT ?
"The Address Part of the Index Addressing mode Instruction must set to zero,to behave like Register Indirect Mode Instruction"IS IT A VALID STATEMENT ?
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1 votes
0 answers
98
Addressing modes
Computer uses addressing modes to reduce number of bits in the addressing field of instruction. Justify this statement and give relevant reasons.
Computer uses addressing modes to reduce number of bits in the addressing field of instruction.Justify this statement and give relevant reasons.
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2 votes
1 answer
102
addressing mode reduces no of bits?
computer uses addressing modes to reduce the number of bits in the addressing field of the instruction Can someone please explain how this statement is true? PLEASE Examples will be helpful
computer uses addressing modes to reduce the number of bits in the addressing field of the instructionCan someone please explain how this statement is true? PLEASEExample...
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2 votes
1 answer
104
Addressing
branch address sign displacement -32. Can anybody explain this line with example? Do it mean target address can be 32 bit before branch address?
branch address sign displacement -32.Can anybody explain this line with example? Do it mean target address can be 32 bit before branch address?
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3 votes
1 answer
105
helpless mind
What is the difference between Base addressing and Index addressing? And finally how does based indexed addressing works?
What is the difference between Base addressing and Index addressing?And finally how does based indexed addressing works?
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1 votes
1 answer
108
UGC NET CSE | June 2009 | Part 2 | Question: 33
In which addressing mode the operand is given explicitly in the instruction itself ? Absolute mode Immediate mode Indirect mode Index mode
In which addressing mode the operand is given explicitly in the instruction itself ?Absolute mode Immediate mode Indirect mode Index mode
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2 votes
1 answer
113
morris-mano addressing mode 3rd edition
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2 votes
1 answer
114
Addressing mode
Self reallocating code required for displacement addressing mode.How ?Please someone explain this concept.
Self reallocating code required for displacement addressing mode.How ?Please someone explain this concept.
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0 votes
1 answer
116
Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 18
Match the pairs about implementation and addressing modes: ... (A-III), (B-I), (C-II) (A-III), (B-II), (C-I) (A-II), (B-III), (C-I)
Match the pairs about implementation and addressing modes:$\begin{array}{|l|l|l|l|} \hline {} & \text{Group A} & {} & \text{Group B} \\ \hline A. & \text{Array} & I. & \t...
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0 votes
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117
Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 14
Match the following: ... -s i-r, ii-s, iii-q, iv-p i-r, ii-s, iii-p, iv-q i-r, ii-p, iii-s, iv-q
Match the following:$\begin{array}{|l|l|l|l|} \hline (i) & \text{Base addressing} & (p) & \text{Pointers} \\ \hline (ii) & \text{Indexed addressing} & (q) & \text{Loops} ...
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2 votes
3 answers
118
Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 9
A two word instruction is stored in memory at an address designated by symbol $S$. The address field of the instruction (stored at $S+1$ ... $P = M [S ] + (K + 2)$ $P = (S + 2) + M [ K ]$
A two word instruction is stored in memory at an address designated by symbol $S$. The address field of the instruction (stored at $S+1$) is designated by symbol K. The o...
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9 votes
2 answers
119
ISRO2017-19
The most appropriate matching for the following pairs : ... $\text{X-ii, Y-iii, Z-i}$ $\text{X-iii, Y-i, Z-ii}$ $\text{X-ii, Y-i, Z-iii}$
The most appropriate matching for the following pairs :$\begin{array}{clcl} \text{X.} & \text{Indirect Addressing} & \text{i.} & \text{Loop} \\ \text{Y.} & \text{Immedi...
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