# Recent questions tagged array-multiplier

The maximum gate delay for any output to appear in an array multiplier for multiplying two $n$ bit numbers is $O(n^2)$ $O(n)$ $O(\log n)$ $O(1)$
Consider an array multiplier for multiplying two $n$ bit numbers. If each gate in the circuit has a unit delay, the total delay of the multiplier is $\Theta(1)$ $\Theta(\log n)$ $\Theta(n)$ $\Theta(n^2)$