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Recent questions tagged assembly
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Recent questions tagged assembly
0
votes
3
answers
1
UGCNET-July-2018-II: 97
Match the items in List-I and List-II ... a-ii, b-i, c-iv a-ii, b-iv, c-iii a-iii, b-i, c-ii a-iii, b-iv, c-ii
Match the items in List-I and List-II ... a-ii, b-i, c-iv a-ii, b-iv, c-iii a-iii, b-i, c-ii a-iii, b-iv, c-ii
asked
Jul 13, 2018
in
CO and Architecture
Pooja Khatri
811
views
ugcnetjuly2018ii
co-and-architecture
assembly
interrupts
0
votes
1
answer
2
UGC NET-PaperIII Nov2017(1)
1.In 8085 microprocessor which of the following flag(s) is (are) affected by an arithmetic operation? (1)AC flag only (2)CY flag only (3)Z flag only (4)AC,CY,Z flags
1.In 8085 microprocessor which of the following flag(s) is (are) affected by an arithmetic operation? (1)AC flag only (2)CY flag only (3)Z flag only (4)AC,CY,Z flags
asked
Nov 6, 2017
in
Digital Logic
mahalakshmi r
1.7k
views
8085
assembly
0
votes
1
answer
3
UGCNET-dec2008-ii-37
An assembly program contains : imperative and declarative statements imperative and assembler directives imperative and declarative statements as well as assembler directives declarative statements and assembler directives
An assembly program contains : imperative and declarative statements imperative and assembler directives imperative and declarative statements as well as assembler directives declarative statements and assembler directives
asked
Sep 26, 2017
in
CO and Architecture
rishu_darkshadow
1.6k
views
ugcnetdec2008ii
co-and-architecture
assembly
0
votes
0
answers
4
GATE1989-6b
In a certain computer system, there is special instruction implemented to call subroutines. The instruction is JSR Reg.Sub Microsequence: Temp ← Sub SP ← (SP)+2 (SP) ← (Reg) Reg ← (PC) PC ← (Temp) Where Temp is an internal CPU register Sub ... you would implement co-routine using the JSR instruction. Show the control flow diagram and the contents of the stack before and after the call.
In a certain computer system, there is special instruction implemented to call subroutines. The instruction is JSR Reg.Sub Microsequence: Temp ← Sub SP ← (SP)+2 (SP) ← (Reg) Reg ← (PC) PC ← (Temp) Where Temp is an internal CPU register Sub is calling ... you would implement co-routine using the JSR instruction. Show the control flow diagram and the contents of the stack before and after the call.
asked
Dec 1, 2016
in
CO and Architecture
makhdoom ghaya
178
views
gate1989
descriptive
co-and-architecture
assembly
unsolved
1
vote
2
answers
5
UGCNET-AUG2016-II: 32
The content of the accumulator after the execution of the following 8085 assembly language program, is MVI A, 35H MOV B, A STC CMC RAR XRA B $00H$ $35H$ $EFH$ $2FH$
The content of the accumulator after the execution of the following 8085 assembly language program, is MVI A, 35H MOV B, A STC CMC RAR XRA B $00H$ $35H$ $EFH$ $2FH$
asked
Sep 26, 2016
in
CO and Architecture
makhdoom ghaya
3.1k
views
ugcnetaug2016ii
co-and-architecture
assembly
8085
1
vote
1
answer
6
UGCNET-Dec2010-II: 35
Macro-processors are ______. Hardware Compiler Registers None of the above
Macro-processors are ______. Hardware Compiler Registers None of the above
asked
Sep 8, 2016
in
CO and Architecture
makhdoom ghaya
1.2k
views
ugcnetdec2010ii
co-and-architecture
assembly
8085
1
vote
1
answer
7
UGCNET-Dec2010-II: 32
'Macro' in an assembly level program is _______. Sub program A complete program A hardware portion Relative coding
'Macro' in an assembly level program is _______. Sub program A complete program A hardware portion Relative coding
asked
Sep 8, 2016
in
CO and Architecture
makhdoom ghaya
1.1k
views
ugcnetdec2010ii
co-and-architecture
assembly
macros
0
votes
2
answers
8
UGCNET-Dec2010-II: 31
Object code is the output of ______. Operating System Compiler or Assembler Only Assembler Only Compiler
Object code is the output of ______. Operating System Compiler or Assembler Only Assembler Only Compiler
asked
Sep 8, 2016
in
CO and Architecture
makhdoom ghaya
432
views
ugcnetdec2010ii
co-and-architecture
assembly
0
votes
1
answer
9
UGCNET-June2011-II: 34
In which way(s) a macroprocessor for assembly language can be implemented? Independent two-pass processor Independent one-pass processor Expand macrocalls and substitute arguments All of the above
In which way(s) a macroprocessor for assembly language can be implemented? Independent two-pass processor Independent one-pass processor Expand macrocalls and substitute arguments All of the above
asked
Aug 30, 2016
in
Others
makhdoom ghaya
526
views
ugcnetjune2011ii
co-and-architecture
microprocessors
assembly
3
votes
2
answers
10
UGCNET-Dec2015-III: 2
What will be the output at $\text{PORT1 }$if the following program is executed? MVI B, 82H MOV A, B MOV C, A MVI D, 37H OUT PORT1 HLT $37H$ $82H$ $B9H$ $00H$
What will be the output at $\text{PORT1 }$if the following program is executed? MVI B, 82H MOV A, B MOV C, A MVI D, 37H OUT PORT1 HLT $37H$ $82H$ $B9H$ $00H$
asked
Aug 9, 2016
in
CO and Architecture
jothee
3.7k
views
ugcnetdec2015iii
8086
assembly
co-and-architecture
non-gate
2
votes
1
answer
11
UGCNET-June2015-III: 3
The RST 7 instruction in 8085 microprocessor is equal to CALL 0010 H CALL 0034 H CALL 0038 H CALL 003C H
The RST 7 instruction in 8085 microprocessor is equal to CALL 0010 H CALL 0034 H CALL 0038 H CALL 003C H
asked
Jul 31, 2016
in
CO and Architecture
jothee
2.1k
views
ugcnetjune2015iii
8085
assembly
language
non-gate
co-and-architecture
1
vote
1
answer
12
UGCNET-June2015-II: 31
Match the following: ... $a-iii, b-iv, c-ii, d-i$ $a-iv, b-i, c-iii, d-ii$ $a-iv, b-iii, c-ii, d-ii$
Match the following: ... $a-iii, b-iv, c-ii, d-i$ $a-iv, b-i, c-iii, d-ii$ $a-iv, b-iii, c-ii, d-ii$
asked
Jul 31, 2016
in
CO and Architecture
jothee
978
views
ugcnetjune2015ii
assembly
0
votes
1
answer
13
UGCNET-Sep2013-III: 33
The instruction : MOV CL, [BX] [DI] + 8 represents the ____ addressing mode Based Relative Based Indexed Indexed Relative Register Indexed
The instruction : MOV CL, [BX] [DI] + 8 represents the ____ addressing mode Based Relative Based Indexed Indexed Relative Register Indexed
asked
Jul 24, 2016
in
CO and Architecture
jothee
1.3k
views
ugcnetsep2013iii
co-and-architecture
assembly
addressing-modes
2
votes
3
answers
14
UGCNET-June2013-III: 44
Interrupt which arises from illegal or erroneous use of an instruction or data is Software interrupt Internal interrupt External interrupt None of the above
Interrupt which arises from illegal or erroneous use of an instruction or data is Software interrupt Internal interrupt External interrupt None of the above
asked
Jul 17, 2016
in
CO and Architecture
jothee
1.4k
views
ugcnetjune2013iii
co-and-architecture
assembly
interrupts
2
votes
1
answer
15
UGCNET-June2013-III: 43
What is not a p typical program control instruction? MR JMP SHL TST
What is not a p typical program control instruction? MR JMP SHL TST
asked
Jul 17, 2016
in
CO and Architecture
jothee
1.4k
views
ugcnetjune2013iii
co-and-architecture
assembly
2
votes
2
answers
16
UGCNET-June2013-III: 42
Computers can have instruction formats with only two address and three address instructions only one address and two address instructions only one address, two address and three address instructions zero address, one address, two address and three address instructions
Computers can have instruction formats with only two address and three address instructions only one address and two address instructions only one address, two address and three address instructions zero address, one address, two address and three address instructions
asked
Jul 17, 2016
in
CO and Architecture
jothee
826
views
ugcnetjune2013iii
co-and-architecture
assembly
3
votes
2
answers
17
UGCNET-June2013-III: 41
Which of the following is not an addressing mode? Register indirect Autoincrement Relative indexed Immediate operand
Which of the following is not an addressing mode? Register indirect Autoincrement Relative indexed Immediate operand
asked
Jul 17, 2016
in
CO and Architecture
jothee
1.4k
views
ugcnetjune2013iii
co-and-architecture
assembly
addressing-modes
0
votes
2
answers
18
UGCNET-June2016-III: 4
The Register that stores all interrupt requests is Interrupt mask register Interrupt service register Interrupt request register Status register
The Register that stores all interrupt requests is Interrupt mask register Interrupt service register Interrupt request register Status register
asked
Jul 11, 2016
in
CO and Architecture
Sanjay Sharma
1.8k
views
ugcnetjune2016iii
co-and-architecture
assembly
0
votes
1
answer
19
assembly code
asked
Jun 10, 2016
in
CO and Architecture
Sourabh Kumar
245
views
assembly
0
votes
0
answers
20
ASSEMBLY
asked
May 11, 2016
in
Programming
Sanjay Sharma
218
views
assembly
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