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Recent questions tagged assembly
3
votes
2
answers
1
GATE Overflow Test Series | Computer Organization and Architecture | Test 1 | Question: 10
Consider the following one address instruction for a hypothetical processor implementing a function: MOVE x MUL x STORE z MOVE x MUL A ADD z ADD B STORE y Which of the following values represents the value of the function if ... $x={10}_{16}$ (Hexadecimal)? $347_{10}$ $176_{10}$ $167_{10}$ $374_{10}$
Consider the following one address instruction for a hypothetical processor implementing a function:MOVE x MUL x STORE z MOVE x MUL A ADD z ADD B STORE yWhich of the foll...
gatecse
333
views
gatecse
asked
Aug 3, 2020
CO and Architecture
go2025-coa-1
easy
assembly
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–
0
votes
4
answers
2
UGC NET CSE | December 2018 | Part 2 | Question: 15
Consider the following $\textsf{x}86$ - assembly language instructions: MOV AL, 153 NEG AL The contents of the destination register $AL$ (in $8$-bit binary notation), th status of Carry Flag $(CF)$ and Sign Flag $(SF)$ ... $AL=0110 \: 0110; \: CF=1; \: SF=1$ $AL=0110 \: 0111; \: CF=1; \: SF=0$
Consider the following $\textsf{x}86$ – assembly language instructions:MOV AL, 153 NEG ALThe contents of the destination register $AL$ (in $8$-bit binary notation), th ...
Arjun
3.9k
views
Arjun
asked
Jan 2, 2019
CO and Architecture
ugcnetcse-dec2018-paper2
co-and-architecture
assembly
non-gate
+
–
0
votes
4
answers
3
UGC NET CSE | July 2018 | Part 2 | Question: 97
Match the items in $\textbf{List-I}$ and $\textbf{List-II}$ ... $\text{(a)-(iii), (b)-(i), (c)-(ii)}$ $\text{(a)-(iii), (b)-(iv), (c)-(ii)}$
Match the items in $\textbf{List-I}$ and $\textbf{List-II}$ :$\begin{array}{clcl} {} & {\textbf{List-I}} & {} & {\textbf{List-II}} \\ \text{(a)} & \text{interrupts whi...
Pooja Khatri
2.6k
views
Pooja Khatri
asked
Jul 13, 2018
CO and Architecture
ugcnetcse-july2018-paper2
co-and-architecture
assembly
interrupts
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–
0
votes
1
answer
4
UGC NET CSE | December 2008 | Part 2 | Question: 37
An assembly program contains : imperative and declarative statements imperative and assembler directives imperative and declarative statements as well as assembler directives declarative statements and assembler directives
An assembly program contains :imperative and declarative statements imperative and assembler directives imperative and declarative statements as...
rishu_darkshadow
7.1k
views
rishu_darkshadow
asked
Sep 26, 2017
CO and Architecture
ugcnetcse-dec2008-paper2
co-and-architecture
assembly
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–
1
votes
0
answers
5
GATE CSE 1989 | Question: 6b
In a certain computer system, there is special instruction implemented to call subroutines. The instruction is JSR Reg.Sub Microsequence: Temp ← Sub SP ← (SP)+2 (SP) ← (Reg) Reg ← (PC) PC ← (Temp) Where Temp is an internal CPU ... would implement co-routine using the JSR instruction. Show the control flow diagram and the contents of the stack before and after the call.
In a certain computer system, there is special instruction implemented to call subroutines. The instruction isJSR Reg.Sub Microsequence: Temp ← Sub SP ← (SP)+2 (SP) �...
makhdoom ghaya
465
views
makhdoom ghaya
asked
Dec 1, 2016
CO and Architecture
gate1989
descriptive
co-and-architecture
assembly
unsolved
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–
1
votes
1
answer
6
UGC NET CSE | August 2016 | Part 2 | Question: 32
The content of the accumulator after the execution of the following 8085 assembly language program, is MVI A, 35H MOV B, A STC CMC RAR XRA B $00H$ $35H$ $EFH$ $2FH$
The content of the accumulator after the execution of the following 8085 assembly language program, isMVI A, 35HMOV B, ASTCCMCRARXRA B$00H$ $35H$$EFH$$2FH$
makhdoom ghaya
6.1k
views
makhdoom ghaya
asked
Sep 26, 2016
CO and Architecture
ugcnetcse-aug2016-paper2
co-and-architecture
assembly
8085-microprocessor
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–
1
votes
1
answer
7
UGC NET CSE | December 2010 | Part 2 | Question: 35
Macro-processors are ______. Hardware Compiler Registers None of the above
Macro-processors are ______.HardwareCompilerRegistersNone of the above
makhdoom ghaya
2.7k
views
makhdoom ghaya
asked
Sep 8, 2016
CO and Architecture
ugcnetcse-dec2010-paper2
co-and-architecture
assembly
8085-microprocessor
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–
1
votes
1
answer
8
UGC NET CSE | December 2010 | Part 2 | Question: 32
'Macro' in an assembly level program is _______. Sub program A complete program A hardware portion Relative coding
'Macro' in an assembly level program is _______.Sub programA complete programA hardware portionRelative coding
makhdoom ghaya
2.2k
views
makhdoom ghaya
asked
Sep 8, 2016
CO and Architecture
ugcnetcse-dec2010-paper2
co-and-architecture
assembly
macros
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–
0
votes
2
answers
9
UGC NET CSE | December 2010 | Part 2 | Question: 31
Object code is the output of ______. Operating System Compiler or Assembler Only Assembler Only Compiler
Object code is the output of ______.Operating SystemCompiler or AssemblerOnly AssemblerOnly Compiler
makhdoom ghaya
1.3k
views
makhdoom ghaya
asked
Sep 8, 2016
CO and Architecture
ugcnetcse-dec2010-paper2
co-and-architecture
assembly
+
–
0
votes
1
answer
10
UGC NET CSE | June 2011 | Part 2 | Question: 34
In which way(s) a macroprocessor for assembly language can be implemented? Independent two-pass processor Independent one-pass processor Expand macrocalls and substitute arguments All of the above
In which way(s) a macroprocessor for assembly language can be implemented?Independent two-pass processorIndependent one-pass processorExpand macrocalls and substitute arg...
makhdoom ghaya
1.0k
views
makhdoom ghaya
asked
Aug 30, 2016
Others
ugcnetcse-june2011-paper2
co-and-architecture
microprocessors
assembly
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–
3
votes
4
answers
11
UGC NET CSE | December 2015 | Part 3 | Question: 2
What will be the output at $\text{PORT1 }$if the following program is executed? MVI B, 82H MOV A, B MOV C, A MVI D, 37H OUT PORT1 HLT $37H$ $82H$ $B9H$ $00H$
What will be the output at $\text{PORT1 }$if the following program is executed?MVI B, 82H MOV A, B MOV C, A MVI D, 37H OUT PORT1 HLT$37H$$82H$$B9H$$00H$
go_editor
8.7k
views
go_editor
asked
Aug 9, 2016
CO and Architecture
ugcnetcse-dec2015-paper3
8086
assembly
co-and-architecture
non-gate
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–
2
votes
1
answer
12
UGC NET CSE | Junet 2015 | Part 3 | Question: 3
The RST 7 instruction in 8085 microprocessor is equal to CALL 0010 H CALL 0034 H CALL 0038 H CALL 003C H
The RST 7 instruction in 8085 microprocessor is equal toCALL 0010 HCALL 0034 HCALL 0038 HCALL 003C H
go_editor
3.7k
views
go_editor
asked
Jul 31, 2016
CO and Architecture
ugcnetcse-june2015-paper3
8085-microprocessor
assembly
language
non-gate
co-and-architecture
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–
1
votes
1
answer
13
UGC NET CSE | Junet 2015 | Part 2 | Question: 31
Match the following: ... $a-iii, b-iv, c-ii, d-i$ $a-iv, b-i, c-iii, d-ii$ $a-iv, b-iii, c-ii, d-ii$
Match the following:$\begin{array}{|ll|ll|} \hline \text{a.} & \text{Forelward Reference Table} & i. & \text{Assembler directive} \\ \hline \text{b.}& \text{Mnemonic Tab...
go_editor
1.7k
views
go_editor
asked
Jul 30, 2016
CO and Architecture
ugcnetcse-june2015-paper2
assembly
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–
0
votes
1
answer
14
UGC NET CSE | September 2013 | Part 3 | Question: 33
The instruction : MOV CL, [BX] [DI] + 8 represents the ____ addressing mode Based Relative Based Indexed Indexed Relative Register Indexed
The instruction : MOV CL, [BX] [DI] + 8 represents the ____ addressing modeBased RelativeBased IndexedIndexed RelativeRegister Indexed
go_editor
2.5k
views
go_editor
asked
Jul 24, 2016
CO and Architecture
ugcnetcse-sep2013-paper3
co-and-architecture
assembly
addressing-modes
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–
2
votes
3
answers
15
UGC NET CSE | June 2013 | Part 3 | Question: 44
Interrupt which arises from illegal or erroneous use of an instruction or data is Software interrupt Internal interrupt External interrupt None of the above
Interrupt which arises from illegal or erroneous use of an instruction or data isSoftware interruptInternal interruptExternal interruptNone of the above
go_editor
3.0k
views
go_editor
asked
Jul 17, 2016
CO and Architecture
ugcnetcse-june2013-paper3
co-and-architecture
assembly
interrupts
+
–
2
votes
1
answer
16
UGC NET CSE | June 2013 | Part 3 | Question: 43
What is not a p typical program control instruction? MR JMP SHL TST
What is not a p typical program control instruction?MRJMPSHLTST
go_editor
2.3k
views
go_editor
asked
Jul 17, 2016
CO and Architecture
ugcnetcse-june2013-paper3
co-and-architecture
assembly
+
–
2
votes
2
answers
17
UGC NET CSE | June 2013 | Part 3 | Question: 42
Computers can have instruction formats with only two address and three address instructions only one address and two address instructions only one address, two address and three address instructions zero address, one address, two address and three address instructions
Computers can have instruction formats withonly two address and three address instructionsonly one address and two address instructionsonly one address, two address and t...
go_editor
1.8k
views
go_editor
asked
Jul 17, 2016
CO and Architecture
ugcnetcse-june2013-paper3
co-and-architecture
assembly
instruction-format
+
–
4
votes
1
answer
18
UGC NET CSE | June 2013 | Part 3 | Question: 41
Which of the following is not an addressing mode? Register indirect Autoincrement Relative indexed Immediate operand
Which of the following is not an addressing mode?Register indirectAutoincrementRelative indexedImmediate operand
go_editor
2.8k
views
go_editor
asked
Jul 17, 2016
CO and Architecture
ugcnetcse-june2013-paper3
co-and-architecture
assembly
addressing-modes
+
–
0
votes
2
answers
19
UGC NET CSE | June 2016 | Part 3 | Question: 4
The Register that stores all interrupt requests is Interrupt mask register Interrupt service register Interrupt request register Status register
The Register that stores all interrupt requests isInterrupt mask registerInterrupt service registerInterrupt request registerStatus register
Sanjay Sharma
3.3k
views
Sanjay Sharma
asked
Jul 11, 2016
CO and Architecture
ugcnetcse-june2016-paper3
co-and-architecture
assembly
+
–
0
votes
1
answer
20
assembly code
Sourabh Kumar
737
views
Sourabh Kumar
asked
Jun 10, 2016
CO and Architecture
assembly
+
–
0
votes
0
answers
21
ASSEMBLY
Sanjay Sharma
381
views
Sanjay Sharma
asked
May 11, 2016
Programming in C
assembly
+
–
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