Recent questions tagged assembly

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2 answers

1

UGCNET-July-2018-II-97
Match the items in List-I and List-II List - I List - II a Interrupts which can be delayed when a much highest priority interrupt has occurred i Normal b Unplanned interrupts which occur while executing a program ii Synchronous c Source of interrupt is in phase with the system clock iii Maskable iv Exception a-ii, b-i, c-iv a-ii, b-iv, c-iii a-iii, b-i, c-ii a-iii, b-iv, c-ii

asked Jul 13, 2018 in Others by Pooja Khatri Boss (10.9k points) | 338 views

0 votes

1 answer

2

UGC NET-PaperIII Nov2017(1)
1.In 8085 microprocessor which of the following flag(s) is (are) affected by an arithmetic operation? (1)AC flag only (2)CY flag only (3)Z flag only (4)AC,CY,Z flags

asked Nov 6, 2017 in Digital Logic by mahalakshmi r (67 points) | 1.4k views

0 votes

1 answer

3

UGCNET-dec2008-ii-37
An assembly program contains: (A) imperative and declarative statements (B) imperative and assembler directives (C) imperative and declarative statements as well as assembler directives (D) declarative statements and assembler directives

asked Sep 26, 2017 in CO and Architecture by rishu_darkshadow Loyal (7.3k points) | 352 views

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0 answers

4

GATE1989-6b
In a certain computer system, there is special instruction implemented to call subroutines. The instruction is JSR Reg.Sub Microsequence: Temp ← Sub SP ← (SP)+2 (SP) ← (Reg) Reg ← (PC) PC ← (Temp) Where Temp is an internal CPU register Sub ... you would implement co-routine using the JSR instruction. Show the control flow diagram and the contents of the stack before and after the call.

asked Dec 1, 2016 in CO and Architecture by makhdoom ghaya Boss (30.8k points) | 120 views

+1 vote

2 answers

5

UGCNET-AUG2016-II-32
The content of the accumulator after the execution of the following 8085 assembly language program, is MVI A, 35H MOV B, A STC CMC RAR XRA B $00H$ $35H$ $EFH$ $2FH$

asked Sep 26, 2016 in CO and Architecture by makhdoom ghaya Boss (30.8k points) | 1.6k views

+1 vote

1 answer

6

UGCNET-Dec2010-II-35
Macro-processors are ______. Hardware Compiler Registers None of the above

asked Sep 8, 2016 in CO and Architecture by makhdoom ghaya Boss (30.8k points) | 514 views

+1 vote

1 answer

7

UGCNET-Dec2010-II-32
'Macro' in an assembly level program is _______. Sub program A complete program A hardware portion Relative coding

asked Sep 8, 2016 in CO and Architecture by makhdoom ghaya Boss (30.8k points) | 432 views

0 votes

2 answers

8

UGCNET-Dec2010-II-31
Object code is the output of ______. Operating System Compiler or Assembler Only Assembler Only Compiler

asked Sep 8, 2016 in CO and Architecture by makhdoom ghaya Boss (30.8k points) | 273 views

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1 answer

9

UGCNET-June2011-II-34
In which way(s) a macroprocessor for assembly language can be implemented? Independent two-pass processor Independent one-pass processor Expand macrocalls and substitute arguments All of the above

asked Aug 30, 2016 in Others by makhdoom ghaya Boss (30.8k points) | 313 views

+2 votes

2 answers

10

UGCNET-Dec2015-II-42
What will be the hexadecimal value in the register $ax$ (32-bit) after executing the following instructions? mov al, 15 mov ah, 15 xor al, al mov cl, 3 shr ax, cl 0F00 h 0F0F h 01E0 h FFFF h

asked Aug 8, 2016 in Others by jothee Veteran (105k points) | 4.5k views

+2 votes

1 answer

11

UGCNET-June2015-III-3
The RST 7 instruction in 8085 microprocessor is equal to CALL 0010 H CALL 0034 H CALL 0038 H CAL 003C H

asked Jul 31, 2016 in Machine Language by jothee Veteran (105k points) | 1.4k views

+1 vote

1 answer

12

UGCNET-June2015-II-31
Match the following: a. Forelward Reference Table i. Assembler directive b. Mnemonic Table ii. Uses array data structure c. Segment Register Table iii. Contains machine OP code d. EQU iv. Uses linked list data structure a-ii, b-iii, c-iv, d-i a-iii, b-iv, c-ii, d-i a-iv, b-i, c-iii, d-ii a-iv, b-iii, c-ii, d-ii

asked Jul 31, 2016 in CO and Architecture by jothee Veteran (105k points) | 500 views

0 votes

1 answer

13

UGCNET-Sep2013-III-33
The instruction : MOV CL, [BX] [DI] + 8 represents the ____ addressing mode Based Relative Based Indexed Indexed Relative Register Indexed

asked Jul 24, 2016 in CO and Architecture by jothee Veteran (105k points) | 711 views

+2 votes

3 answers

14

UGCNET-June2013-III-44
Interrupt which arises from illegal or erroneous use of an instruction or data is Software interrupt Internal interrupt External interrupt None of the above

asked Jul 17, 2016 in Others by jothee Veteran (105k points) | 972 views

+2 votes

1 answer

15

UGCNET-June2013-III-43
What is not a p typical program control instruction? MR JMP SHL TST

asked Jul 17, 2016 in Others by jothee Veteran (105k points) | 812 views

+2 votes

2 answers

16

UGCNET-June2013-III-42
Computers can have instruction formats with only two address and three address instructions only one address and two address instructions only one address, two address and three address instructions zero address, one address, two address and three address instructions

asked Jul 17, 2016 in Others by jothee Veteran (105k points) | 473 views

+3 votes

2 answers

17

UGCNET-June2013-III-41
Which of the following is not an addressing mode? Register indirect Autoincrement Relative indexed Immediate operand

asked Jul 17, 2016 in Others by jothee Veteran (105k points) | 706 views

0 votes

1 answer

18

UGCNET-June2016-III-4
The Register that stores all interrupt requests is Interrupt mask register Interrupt service register Interrupt request register Status register

asked Jul 11, 2016 in CO and Architecture by Sanjay Sharma Boss (49.3k points) | 1.5k views

0 votes

1 answer

19

assembly code

asked Jun 10, 2016 in CO and Architecture by Sourabh Kumar Active (1.5k points) | 163 views

0 votes

0 answers

20

ASSEMBLY

asked May 11, 2016 in Programming by Sanjay Sharma Boss (49.3k points) | 199 views

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content	content:apple
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force match	+apple
views	views:100
score	score:10
answers	answers:2
is accepted	isaccepted:true
is closed	isclosed:true

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