Recent questions tagged branch-conditional-instructions / GATE Overflow for GATE CSE

0 votes

1 answer

31

Branch Instruction
What is meaning of offset in Branch instruction? Is this offset same as conditional instruction offset? What is meaning of offset in virtual address? Where is actual difference between these two?

What is meaning of offset in Branch instruction? Is this offset same as conditional instruction offset?What is meaning of offset in virtual address? Where is actual diffe...

srestha

500 views

srestha asked Jun 10, 2018

1 votes

0 answers

32

[Self Doubt] previous year explanation
https://gateoverflow.in/683/gate2000-12 Can you please explain the meaning of the highlighted portion of the text. This is an explanation by Arjun Sir

https://gateoverflow.in/683/gate2000-12Can you please explain the meaning of the highlighted portion of the text. This is an explanation by Arjun Sir

Anshul Shankar

225 views

Anshul Shankar asked Nov 23, 2017

5 votes

3 answers

33

Implementation of BSA(Branch and save address) instruction
I have a doubt regarding the implementation of BSA instruction. I read that BSA instruction can be implemented as :- T4:- m[AR] <-- PC; AR<--AR+1 T5:- PC<--AR; SC<--0 Here T4 and T5 are 4th and ... to the position where PC is written. So they should happen at different clock cycles right so that they can execute in proper order?

I have a doubt regarding the implementation of BSA instruction. I read that BSA instruction can be implemented as :-T4:- m[AR] < PC; AR< AR+1T5:- PC< AR; SC< 0He...

Xylene

3.2k views

Xylene asked Jun 6, 2017

5 votes

1 answer

34

COA pipeline doubt
I) In a 4 stage pipeline processor, if each stage takes 4 cycles then what is CPI in case of successfull pipeline??? II) In a 4 stage pipeline processor, if each stage takes 2,3,4,5 cycles respectively then what is CPI in case ... are branch imstructions and branch address is available in 3rd stage then what should be branch pelanty??(In both the implementations mentioned above)

I) In a 4 stage pipeline processor, if each stage takes 4 cycles then what is CPI in case of successfull pipeline???II) In a 4 stage pipeline processor, if each stage tak...

Rahul Jain25

947 views

Rahul Jain25 asked Feb 5, 2017

0 votes

0 answers

35

Computer Architecture and Organisation
Q No: 48 The access time of cache memory is 15 ns and main memory is 100 ns. It is also estimated that 70% of memory requests are for read and remaining are for write. The list ratio for read access is only 80%. A write through ... write operation, pages are always available in cache so the total access time (in ns) is? Correct Answer: 54.5 Status: unattempted

Q No: 48 The access time of cache memory is 15 ns and main memory is 100 ns. It is also estimated that 70% of memory requests are for read and remaining are for write. T...

vishwa ratna

439 views

vishwa ratna asked Jan 18, 2017

6 votes

3 answers

36

Computer Architecture Pipelining

Çșȇ ʛấẗẻ

2.4k views

Çșȇ ʛấẗẻ asked Jan 4, 2017

1 votes

1 answer

37

conditional and unconditional branch
can someone explain the diff between conditional and unconitional branch with some pipeline diagram or example??

can someone explain the diff between conditional and unconitional branch with some pipeline diagram or example??

Akriti sood

9.7k views

Akriti sood asked Nov 3, 2016

6 votes

3 answers

38

Pipelining
Consider a 4 stage pipeline where the branch is resolved at the end of the second cycle for unconditional branches and at the end of the third cycle for the conditional branches. Assume that no instruction starts at first stage time the branch condition is evaluated. Let the branch ... stalls how much faster would the machine be without any branch hazards? a)0.729 b)0.459 c)0.689 d)1.45

Consider a 4 stage pipeline where the branch is resolved at the end of the second cycle for unconditional branches and at the end of the third cycle for the conditional b...

Amit puri

5.2k views

Amit puri asked Aug 17, 2016

2 votes

2 answers

39

pipelining
Q31). Consider a pipeline "x" consist of $5$ stages names as $IF$,$ID$,$OF$,$EX$ and $WB$ with the respective stage delays of $2 \text{ns}$ ,$5 \text{ns}$, $6 \text{ns}$ and $1 \text{ns}$ .The alternative pipeline ... of the instructions which are memory based instructions, the speedup ratio of 'x' is speedup ratio of 'y' is _______ please elaborate on it ?

Q31). Consider a pipeline "x" consist of $5$ stages names as $IF$,$ID$,$OF$,$EX$ and $WB$ with the respective stage delays of $2 \text{ns}$ ,$5 \text{ns}$, $6 \text{ns}$ ...

nitish

664 views

nitish asked Jan 21, 2016

1 votes

2 answers

40

pipelining - branch delay slot

Himanshu1

1.4k views

Himanshu1 asked Dec 24, 2015

0 votes

1 answer

41

Q-26 ch-4 Branch conditional instruction
Among the branch instructions 30% conditional and 70% of them does not satisfy the condition ( branch not taken). If there is no stall due to them. What is average instruction execution time. A. 28.96ns b. 30.2 ns c. 32.27 ns d. 38.96ns

Among the branch instructions 30% conditional and 70% of them does not satisfy the condition ( branch not taken). If there is no stall due to them. What is average instru...

khushtak

1.1k views

khushtak asked Oct 19, 2015

1 votes

0 answers

42

Conditional branch instruction
An instruction pipeline has 5 stages where each stage takes 2 ns and all instructions use all 5 stages. Branch instructions are not overlapped i.e. the instruction after branch is not fetched till the branch instruction is completed consider ideal conditions. If ... is taken calculate average instruction execution time. A. 5.26 ns b. 2.96ns c. 4.26ns d. 2.36ns

An instruction pipeline has 5 stages where each stage takes 2 ns and all instructions use all 5 stages. Branch instructions are not overlapped i.e. the instruction after ...

khushtak

1.8k views

khushtak asked Oct 19, 2015

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