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A Simple Illustration
Cache Memory
Recent questions tagged cache-memory
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GATE CSE 2024 | Set 1 | Question: 43
Consider two set-associative cache memory architectures: $\text{WBC}$, which uses the write back policy, and $\text{WTC}$, which uses the write through policy. Both of them use the $\text{LRU}$ (Least Recently Used) block ... write miss in $\text{WTC}$ always writes the victim cache block to main memory before loading the missed block to the cache
Consider two set-associative cache memory architectures: $\text{WBC}$, which uses the write back policy, and $\text{WTC}$, which uses the write through policy...
Arjun
2.1k
views
Arjun
asked
Feb 16
CO and Architecture
gatecse2024-set1
co-and-architecture
cache-memory
multiple-selects
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4
votes
1
answer
2
GO Classes Test Series 2024 | Mock GATE | Test 14 | Question: 55
Consider the cache of size 512 bytes that is direct-mapped? Suppose the size of integer is 4 bytes and block size is 16 bytes. Assume cache is initially empty and all data except for the array x are stored in registers, and that the ... ) { sum += x[i]; } What is the miss rate for the above loop? (roundoff to two decimal places)
Consider the cache of size 512 bytes that is direct-mapped?Suppose the size of integer is 4 bytes and block size is 16 bytes. Assume cache is initially empty and all data...
GO Classes
447
views
GO Classes
asked
Feb 5
CO and Architecture
goclasses2024-mockgate-14
numerical-answers
co-and-architecture
cache-memory
page-fault
2-marks
+
–
6
votes
1
answer
3
GO Classes Test Series 2024 | Mock GATE | Test 13 | Question: 54
Assume a cache memory with the following properties: The cache size $\text{(C)}$ is 512 bytes (contains $512$ data bytes) The cache uses an LRU (least recently used) policy for eviction. The cache is initially empty. Suppose that for the following ... cache? $\text{B}=4$ bytes $\text{B}=8$ bytes $\text{B}=16$ bytes None of the above.
Assume a cache memory with the following properties:The cache size $\text{(C)}$ is 512 bytes (contains $512$ data bytes)The cache uses an LRU (least recently used) policy...
GO Classes
743
views
GO Classes
asked
Jan 28
CO and Architecture
goclasses2024-mockgate-13
goclasses
co-and-architecture
cache-memory
2-marks
+
–
3
votes
2
answers
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GO Classes Test Series 2024 | Mock GATE | Test 12 | Question: 5
Suppose we have a four-way set associative physically addressed cache of size $256 \mathrm{KB}$ and $\text{16B}$ blocks, on a machine that uses $32$-bit physical addresses. How many bits will be used for the index?
Suppose we have a four-way set associative physically addressed cache of size $256 \mathrm{KB}$ and $\text{16B}$ blocks, on a machine that uses $32$-bit physical addresse...
GO Classes
521
views
GO Classes
asked
Jan 21
CO and Architecture
goclasses2024-mockgate-12
goclasses
numerical-answers
co-and-architecture
cache-memory
1-mark
+
–
8
votes
1
answer
5
GO Classes Test Series 2024 | Mock GATE | Test 12 | Question: 50
A computer has a $32$-bit address bus with a direct mapped cache, using $4$ bits for block offset, $16$ tag bits, and $12$ index bits. Which of the following address pairs can be placed in the cache simultaneously? $\textsf{3AC6 F45 6}$ ... $\textsf{5E3C 768 0}$ and $\textsf{8F3C 768 A}$ $\textsf{2233 445 5}$ and $\textsf{2233 445 C}$
A computer has a $32$-bit address bus with a direct mapped cache, using $4$ bits for block offset, $16$ tag bits, and $12$ index bits.Which of the following address pairs...
GO Classes
836
views
GO Classes
asked
Jan 21
CO and Architecture
goclasses2024-mockgate-12
goclasses
co-and-architecture
cache-memory
multiple-selects
2-marks
+
–
5
votes
1
answer
6
GO Classes Test Series 2024 | Mock GATE | Test 11 | Question: 34
Which of the following is the best justification for using the middle bits of an address as the set index into a cache rather than the most significant bits? Indexing with the most significant bits would necessitate a smaller ... is likely to make more efficient use of the cache with middle-bit indexing than with high-bit indexing.
Which of the following is the best justification for using the middle bits of an address as the set index into a cache rather than the most significant bits?Indexing with...
GO Classes
428
views
GO Classes
asked
Jan 13
CO and Architecture
goclasses2024-mockgate-11
goclasses
co-and-architecture
cache-memory
1-mark
+
–
0
votes
3
answers
7
Made Easy Test Series 2024
Can anyone please confirm that below statement is correct or not : - Statement 3 is false for Only Full Associative cache mapping and for direct and set associative mapping Statement 3 is True Because of this concept(Answer) https://gateoverflow.in/409971/made-easy-test-series-2024
Can anyone please confirm that below statement is correct or not : -Statement 3 is false for Only Full Associative cache mapping and for direct and set associative map...
Ray Tomlinson
505
views
Ray Tomlinson
asked
Sep 5, 2023
CO and Architecture
direct-mapping
cache-memory
co-and-architecture
+
–
0
votes
0
answers
8
Hit Latency | Computer Organization
is this formula is correct if it is correct then in gate 2006 Question 75 why they not used this formula https://gateoverflow.in/43565/gate-cse-2006-question-75
is this formula is correct if it is correct then in gate 2006 Question 75 why they not used this formulahttps://gateoverflow.in/43565/gate-cse-2006-question-75
Ray Tomlinson
240
views
Ray Tomlinson
asked
Aug 22, 2023
CO and Architecture
co-and-architecture
cache-memory
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0
votes
1
answer
9
Computer Organisation Textbook Questions
Consider the case memory which has 0.8 and 0.9 hit ratio for read and write operation. Whenever there exist here miss either read or write 2 word block is to be moved from main memory to case memory. The case access time is ... time for read operation, 2. second find average access time for write operation, 3. average access time overall and throughput.
Consider the case memory which has 0.8 and 0.9 hit ratio for read and write operation. Whenever there exist here miss either read or write 2 word block is to be moved fro...
Ray Tomlinson
464
views
Ray Tomlinson
asked
Aug 19, 2023
CO and Architecture
co-and-architecture
reference-book
cache-memory
carl-hamacher
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