Recent questions tagged cache-memory

+1 vote

0 answers

1

Caching
Given the following information: TLB hit rate 95%, TLB access time is 1 cycle. cache hit rate 90 %, cache access time is 1 cycle. When TLB and cache both get miss; page fault rate is 1% The TLB access and acache access are ... cycles Access to hard drive requires 50,000 cycles. Compute the average memory access latencies when the cache is physically addresses (in cycles).

asked Mar 10 in CO and Architecture by s_dr_13 (133 points) | 65 views

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1 answer

2

Self doubt(Hamacher and Zaky)
Memory is word addressable with 16 bit addresses Word size=16 bits Each block is of size 16 bits. The cache contains 8 blocks. What is the address division for: 1>direct. 2>associative 3>set associative cache

asked Feb 17 in CO and Architecture by DIYA BASU (227 points) | 58 views

+1 vote

6 answers

3

GATE2019-1
A certain processor uses a fully associative cache of size $16$ kB, The cache block size is $16$ bytes. Assume that the main memory is byte addressable and uses a $32$-bit address. How many bits are required for the Tag and the Index fields respectively in the addresses generated by the processor? $24$ bits and $0$ bits $28$ bits and $4$ bits $24$ bits and $4$ bits $28$ bits and $0$ bits

asked Feb 7 in CO and Architecture by Arjun Veteran (413k points) | 3.5k views

+2 votes

7 answers

4

GATE2019-45
A certain processor deploys a single-level cache. The cache block size is $8$ words and the word size is $4$ bytes. The memory system uses a $60$-MHz clock. To service a cache miss, the memory controller first takes $1$ cycle to accept the ... bandwidth for the memory system when the program running on the processor issues a series of road operations is ______$\times 10^6$ bytes/sec

asked Feb 7 in CO and Architecture by Arjun Veteran (413k points) | 2.1k views

0 votes

0 answers

5

ME adv mock
A hypothetical processor on cache read miss requires one clock to send an address to Main Memory (MM) and eight clock cycles to access a 64-bit word from MM to processor cache. Miss rate of read is decreased from 14.8% to 2.6% when line size ... words. The speed up of processor is achieved in dealing with average read miss after increasing the line size is_____ (Upto 2 decimal places)

asked Feb 1 in CO and Architecture by newdreamz a1-z0 Active (1.5k points) | 71 views

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1 answer

6

GRADEUP
For a 4 bit set associative cache 10 bits are required as index to specify cache block. The main memory is of size 4G x 32. Size of cache memory is? Answer is 4096*49. Please explain the notation also.

asked Feb 1 in CO and Architecture by Aman Janko (49 points) | 59 views

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7

computer organization
Consider the hypothetical processor is supports both 2 address and one address instructions. It has 128-word memory A 16-bit instruction is placed in the one memory word. Q1.What is the range of two address and one address instructions are supported? A)1 to ... instructions can be supported? A)128 B)2 C)256 D)32 PLEASE GIVE SOLUTION IN DETAILED MANNER...ESPECIALLY FOR PART 1.

asked Feb 1 in CO and Architecture by learner_geek Active (3.1k points) | 143 views

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1 answer

8

MadeEasy Test Series 2019: CO & Architecture- Cache Memory
Consider a n-way cache with 'x blocks of 64 words each. The main memory of the system is having 8 million words. Size of the tag field is 16 bits and additional memory required for tags is 1024 bytes. What will be the values of n and x respectively? Answer 256 512

asked Jan 30 in CO and Architecture by Ram Swaroop Active (3.5k points) | 160 views

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1 answer

9

MadeEasy Test Series 2019: CO & Architecture - Cache Memory
A CPU cache is organized into 2 level cache L1 and L2 The penalty for L1 cache miss and L2 cache miss are 60 and 30 respectively for 1200 memory references The hit time of L1 and L2 are 5 and 10 clock cycles and penalty for L2 cache miss to main memory is 70 clock cycles. The average memory access time will be

asked Jan 29 in CO and Architecture by Ram Swaroop Active (3.5k points) | 125 views

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0 answers

10

MadeEasy Full Length Test 2019: CO & Architecture - Cache Memory
Consider a 2 way set associative cache with 4 blocks. The memory block requests in the order. 4,6,3,8,5,6,0,15,6,17,20,15,0,8 If LRU is used for block replacement then memory set 17 will be in the cache block ____. (PS: the given answer is 1)

asked Jan 28 in CO and Architecture by snaily16 (239 points) | 84 views

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11

Computer organisation cache
Why can't we have n-levels of cache ?

asked Jan 27 in CO and Architecture by Priyansh Singh (341 points) | 64 views

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1 answer

12

Cache Organization
Can any one help me out with this question : This was asked in MadeEasy CBT held on 23rd jan

asked Jan 25 in CO and Architecture by Nandkishor3939 Active (1.1k points) | 143 views

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0 answers

13

MadeEasy Full Length Test 2019: CO & Architecture - Cache Memory
All is fine but how did they calculate the miss rate of level 2 cache (L2) i.e.how is m2=0.46875?

asked Jan 24 in CO and Architecture by Iamniks4 (31 points) | 60 views

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1 answer

14

Ace Test Series: CO & Architecture - Cache Memory

asked Jan 21 in CO and Architecture by Na462 Loyal (6.6k points) | 89 views

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0 answers

15

Ace Test Series: CO & Architecture - Cache Misses Type

asked Jan 21 in CO and Architecture by Na462 Loyal (6.6k points) | 110 views

+1 vote

0 answers

16

GATEBOOK-2019 Mock Test1-42
Consider a memory system with a cache access time of $10 \: ns$ and a memory access time of $110 \: ns$ – assume the memory access time includes the time to check the cache. If the effective access time is $10\%$ greater than the cache access time and if the hit ratio $H$ is $x/100$ then $x$ is ____ $95$ $99$ $89$ None of these

asked Jan 19 in CO and Architecture by GATEBOOK Boss (11.4k points) | 138 views

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0 answers

17

find conflict misses
here it is given byte addressable. So these locations refer to words or byte location. What are set, block fields here : number of words or number of bytes for these location.

asked Jan 18 in CO and Architecture by bts1jimin (193 points) | 48 views

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18

Computer system organization cache memory
Assume that A, B , and C are memory addresses each of which are in different block of memory. Further assume A, B , C are generated in a uniformly random way. What is the probability that the second instance of "B" will be a hit on a 4-line direct-mapped cache?

asked Jan 16 in CO and Architecture by Nikita Shadija (5 points) | 43 views

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1 answer

19

Ace Test Series 2019: CO & Architecture - Cache Memory Tag Size

asked Jan 14 in CO and Architecture by Shankar Kakde (147 points) | 56 views

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20

Self doubt about LRU and Direct mapping cache
Can we apply LRU policy to direct mapped cache. according to me it doesn't make any sense as eventually it will be like FIFO only as unique memory addresses are assigned to each cache line. But my doubt / confusion is can we implement LRU on direct mapped caches?

asked Jan 12 in CO and Architecture by S Ram Active (1.7k points) | 33 views

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21

VIRTUAL GATE TEST SERIES

asked Jan 11 in CO and Architecture by Ajay Maurya 6 (327 points) | 48 views

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1 answer

22

MadeEasy Test Series: CO & Architecture - Cache Memory

asked Jan 10 in CO and Architecture by Shubham Kumar Gupta (443 points) | 90 views

+1 vote

0 answers

23

MadeEasy Test Series: CO & Architecture - Cache Memory
A hypothetical processor on cache read miss requires one clock to send an address to Main Memory (MM) and eight clock cycles to access a 64-bit word from MM to processor cache. Miss rate of read is decreased from 14.8% to ... up of processor is achieved in dealing with average read miss after increasing the line size is (Upto 2 decimal places)

asked Jan 9 in CO and Architecture by Jay Bhutada 1 (181 points) | 97 views

0 votes

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24

GATE 2019 2-way set associative
plz explain …..??

asked Jan 7 in Operating System by Vikas123 (333 points) | 88 views

0 votes

1 answer

25

MadeEasy Test Series: CO & Architecture - Cache Memory
A CPU has recorded 450 memory references. The CPU has been organized into 2-level of cache memory L1 and L2 . There are 50 misses and 25 misses in L1 and L2 respectively. The miss penalty from L2 cache to memory is 60 cycles and hit time of L2 cache is 30 cycles. What is the average stall (in cycles) per instruction.? 20 40 80 32

asked Jan 7 in CO and Architecture by Shivam Kasat Active (3.1k points) | 139 views

0 votes

1 answer

26

MadeEasy Test Series: CO & Architecture - Cache Memory

asked Jan 7 in CO and Architecture by jatin khachane 1 Loyal (6.7k points) | 52 views

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0 answers

27

MADEEASY- CO - SET Associative mapping
Assume a new cache design is proposed by a student. But he later discovered design has too many conflict misses and to resolve this issue he increases the associativity in the design. Which of the following implication will occur in the ... bit increases C. No implications in the design what does INDEX bits refers to in set associative and associative mapping?

asked Dec 29, 2018 in CO and Architecture by Markzuck Junior (571 points) | 73 views

0 votes

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28

MadeEasy Test Series: CO & Architecture - Cache Memory
Consider the following statements: S1: Direct mapped caches do not need a cache block replacement policy, where as fully associative cache need. S2:: Direct mapped cache, may produce more misses if programs refers to memory words that occupy a same tag value. Which of the following options is correct? How S1 is true?

asked Dec 28, 2018 in CO and Architecture by Shivam Kasat Active (3.1k points) | 97 views

+6 votes

0 answers

29

GO2019-FLT1-41
Consider a Computer system with a single core CPU, a single level of cache of size $4 \text{MB}$, and main memory. It takes one CPU cycle to access a memory byte if it is in cache, and $145$ cycles if the memory access incurs a cache miss and must be fetched from main memory. The ... of $A$ and $B$ is read in sequence as follows: for (i=0;i<N;i++) { read A[i]; read B{i]; }

asked Dec 27, 2018 in CO and Architecture by Ruturaj Mohanty Active (2.5k points) | 242 views

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