Recent questions tagged cache-memory - GATE Overflow

+5 votes

3 answers

1

GATE2020-CS-30
A computer system with a word length of $32$ bits has a $16$ MB byte- addressable main memory and a $64$ KB, $4$-way set associative cache memory with a block size of $256$ ... cache set. $A3$ and $A4$ are mapped to the same cache set. $A1$ and $A3$ are mapped to the same cache set.

asked Feb 12 in CO and Architecture by Arjun | 1.6k views

+4 votes

2 answers

2

ISRO2020-47
How many total bits are required for a direct-mapped cache with $128$ KB of data and $1$ word block size, assuming a $32$-bit address and $1$ word size of $4$ bytes? $2$ Mbits $1.7$ Mbits $2.5$ Mbits $1.5$ Mbits

asked Jan 14 in CO and Architecture by Satbir | 602 views

+1 vote

2 answers

3

ISRO2020-43
Which of the following is an efficient method of cache updating? Snoopy writes Write through Write within Buffered write

asked Jan 13 in CO and Architecture by Satbir | 485 views

0 votes

0 answers

4

Andrew S. Tanenbaum (OS) Edition 4 Exercise 4 Question 32 (Page No. 335)
The performance of a file system depends upon the cache hit rate (fraction of blocks found in the cache). If it takes $1\: msec$ to satisfy a request from the cache, but $40\: msec$ to satisfy a request if a disk read is needed ... request if the hit rate is $h.$ Plot this function for values of $h$ varying from $0$ to $1.0.$

asked Oct 27, 2019 in Operating System by Lakshman Patel RJIT | 51 views

0 votes

0 answers

5

Andrew S. Tanenbaum (OS) Edition 4 Exercise 2 Question 10 (Page No. 174)
In the text it was stated that the model of Fig. $2-11(a)$ was not suited to a file server using a cache in memory. Why not? Could each process have its own cache?

asked Oct 25, 2019 in Operating System by Lakshman Patel RJIT | 27 views

0 votes

2 answers

6

Andrew S. Tanenbaum (OS) Edition 4 Exercise 1 Question 4 (Page No. 81)
To use cache memory, main memory is divided into cache lines, typically $32$ or $64$ bytes long. An entire cache line is cached at once. What is the advantage of caching an entire line instead of a single byte or word at a time?

asked Oct 21, 2019 in Operating System by Lakshman Patel RJIT | 70 views

+1 vote

0 answers

7

Caching
Given the following information: TLB hit rate 95%, TLB access time is 1 cycle. cache hit rate 90 %, cache access time is 1 cycle. When TLB and cache both get miss; page fault rate is 1% The TLB access and acache access are ... cycles Access to hard drive requires 50,000 cycles. Compute the average memory access latencies when the cache is physically addresses (in cycles).

asked Mar 11, 2019 in CO and Architecture by s_dr_13 | 204 views

0 votes

1 answer

8

Self doubt(Hamacher and Zaky)
Memory is word addressable with 16 bit addresses Word size=16 bits Each block is of size 16 bits. The cache contains 8 blocks. What is the address division for: 1>direct. 2>associative 3>set associative cache

asked Feb 17, 2019 in CO and Architecture by DIYA BASU | 149 views

+9 votes

7 answers

9

GATE2019-1
A certain processor uses a fully associative cache of size $16$ kB, The cache block size is $16$ bytes. Assume that the main memory is byte addressable and uses a $32$-bit address. How many bits are required for the Tag and the Index fields respectively in the addresses generated by the processor? $24$ bits and $0$ bits $28$ bits and $4$ bits $24$ bits and $4$ bits $28$ bits and $0$ bits

asked Feb 7, 2019 in CO and Architecture by Arjun | 6.3k views

+19 votes

8 answers

10

GATE2019-45
A certain processor deploys a single-level cache. The cache block size is $8$ words and the word size is $4$ bytes. The memory system uses a $60$-MHz clock. To service a cache miss, the memory controller first takes $1$ cycle to accept the ... bandwidth for the memory system when the program running on the processor issues a series of read operations is ______$\times 10^6$ bytes/sec

asked Feb 7, 2019 in CO and Architecture by Arjun | 4.8k views

+2 votes

0 answers

11

ME adv mock
A hypothetical processor on cache read miss requires one clock to send an address to Main Memory (MM) and eight clock cycles to access a 64-bit word from MM to processor cache. Miss rate of read is decreased from 14.8% to 2.6% when line size ... words. The speed up of processor is achieved in dealing with average read miss after increasing the line size is_____ (Upto 2 decimal places)

asked Feb 1, 2019 in CO and Architecture by newdreamz a1-z0 | 153 views

0 votes

1 answer

12

GRADEUP
For a 4 bit set associative cache 10 bits are required as index to specify cache block. The main memory is of size 4G x 32. Size of cache memory is? Answer is 4096*49. Please explain the notation also.

asked Feb 1, 2019 in CO and Architecture by Aman Janko | 149 views

0 votes

1 answer

13

computer organization
Consider the hypothetical processor is supports both 2 address and one address instructions. It has 128-word memory A 16-bit instruction is placed in the one memory word. Q1.What is the range of two address and one address instructions are supported? A)1 to ... instructions can be supported? A)128 B)2 C)256 D)32 PLEASE GIVE SOLUTION IN DETAILED MANNER...ESPECIALLY FOR PART 1.

asked Feb 1, 2019 in CO and Architecture by learner_geek | 627 views

+3 votes

1 answer

14

MadeEasy Test Series 2019: CO & Architecture- Cache Memory
Consider a n-way cache with 'x blocks of 64 words each. The main memory of the system is having 8 million words. Size of the tag field is 16 bits and additional memory required for tags is 1024 bytes. What will be the values of n and x respectively? Answer 256 512

asked Jan 30, 2019 in CO and Architecture by Ram Swaroop | 355 views

+2 votes

1 answer

15

MadeEasy Test Series 2019: CO & Architecture - Cache Memory
A CPU cache is organized into 2 level cache L1 and L2 The penalty for L1 cache miss and L2 cache miss are 60 and 30 respectively for 1200 memory references The hit time of L1 and L2 are 5 and 10 clock cycles and penalty for L2 cache miss to main memory is 70 clock cycles. The average memory access time will be

asked Jan 29, 2019 in CO and Architecture by Ram Swaroop | 343 views

0 votes

0 answers

16

MadeEasy Full Length Test 2019: CO & Architecture - Cache Memory
Consider a 2 way set associative cache with 4 blocks. The memory block requests in the order. 4,6,3,8,5,6,0,15,6,17,20,15,0,8 If LRU is used for block replacement then memory set 17 will be in the cache block ____. (PS: the given answer is 1)

asked Jan 28, 2019 in CO and Architecture by snaily16 | 197 views

0 votes

0 answers

17

Computer organisation cache
Why can't we have n-levels of cache ?

asked Jan 27, 2019 in CO and Architecture by Priyansh Singh | 113 views

0 votes

1 answer

18

Cache Organization
Can any one help me out with this question : This was asked in MadeEasy CBT held on 23rd jan

asked Jan 26, 2019 in CO and Architecture by Nandkishor3939 | 230 views

0 votes

1 answer

19

MadeEasy Full Length Test 2019: CO & Architecture - Cache Memory
All is fine but how did they calculate the miss rate of level 2 cache (L2) i.e.how is m2=0.46875?

asked Jan 24, 2019 in CO and Architecture by Iamniks4 | 165 views

+1 vote

1 answer

20

Ace Test Series: CO & Architecture - Cache Memory

asked Jan 22, 2019 in CO and Architecture by Na462 | 188 views

+1 vote

0 answers

21

Ace Test Series: CO & Architecture - Cache Misses Type

asked Jan 22, 2019 in CO and Architecture by Na462 | 266 views

0 votes

0 answers

22

find conflict misses
here it is given byte addressable. So these locations refer to words or byte location. What are set, block fields here : number of words or number of bytes for these location.

asked Jan 18, 2019 in CO and Architecture by bts1jimin | 125 views

0 votes

0 answers

23

Computer system organization cache memory
Assume that A, B , and C are memory addresses each of which are in different block of memory. Further assume A, B , C are generated in a uniformly random way. What is the probability that the second instance of "B" will be a hit on a 4-line direct-mapped cache?

asked Jan 16, 2019 in CO and Architecture by Nikita Shadija | 80 views

0 votes

1 answer

24

Ace Test Series 2019: CO & Architecture - Cache Memory Tag Size

asked Jan 14, 2019 in CO and Architecture by Shankar Kakde | 127 views

0 votes

0 answers

25

Self doubt about LRU and Direct mapping cache
Can we apply LRU policy to direct mapped cache. according to me it doesn't make any sense as eventually it will be like FIFO only as unique memory addresses are assigned to each cache line. But my doubt / confusion is can we implement LRU on direct mapped caches?

asked Jan 12, 2019 in CO and Architecture by S Ram | 79 views

0 votes

0 answers

26

VIRTUAL GATE TEST SERIES

asked Jan 11, 2019 in CO and Architecture by Ajay Maurya 6 | 86 views

+1 vote

1 answer

27

MadeEasy Test Series: CO & Architecture - Cache Memory

asked Jan 10, 2019 in CO and Architecture by Shubham Kumar Gupta | 183 views

+1 vote

0 answers

28

MadeEasy Test Series: CO & Architecture - Cache Memory
A hypothetical processor on cache read miss requires one clock to send an address to Main Memory (MM) and eight clock cycles to access a 64-bit word from MM to processor cache. Miss rate of read is decreased from 14.8% to ... up of processor is achieved in dealing with average read miss after increasing the line size is (Upto 2 decimal places)

asked Jan 10, 2019 in CO and Architecture by Jay Bhutada 1 | 189 views

0 votes

0 answers

29

GATE 2019 2-way set associative
plz explain …..??

asked Jan 8, 2019 in Operating System by Vikas123 | 132 views

0 votes

1 answer

30

MadeEasy Test Series: CO & Architecture - Cache Memory
A CPU has recorded 450 memory references. The CPU has been organized into 2-level of cache memory L1 and L2 . There are 50 misses and 25 misses in L1 and L2 respectively. The miss penalty from L2 cache to memory is 60 cycles and hit time of L2 cache is 30 cycles. What is the average stall (in cycles) per instruction.? 20 40 80 32

asked Jan 8, 2019 in CO and Architecture by Shivam Kasat | 288 views

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