Login
Register
@
Dark Mode
Profile
Edit my Profile
Messages
My favorites
Register
Activity
Q&A
Questions
Unanswered
Tags
Subjects
Users
Ask
Previous Years
Blogs
New Blog
Exams
Dark Mode
Slides
A Simple Illustration
Cache Memory
Recent questions tagged cache-memory
1
vote
3
answers
1
GATE CSE 2023 | Question: 54
An $8$-way set associative cache of size $64 \mathrm{~KB} \;(1 \mathrm{~KB}=1024\; \text{bytes})$ is used in a system with $32$-bit address. The address is sub-divided into $\text{TAG, INDEX},$ and $\text{BLOCK OFFSET.}$ The number of bits in the $\text{TAG}$ is ___________.
admin
asked
in
CO and Architecture
Feb 15
by
admin
1.1k
views
gatecse-2023
co-and-architecture
cache-memory
numerical-answers
2-marks
0
votes
1
answer
2
#COA #CacheMemory
What is the default access method of Cache Memory? Simultaneous or Hierarchical?
iamsubhrajit
asked
in
CO and Architecture
Dec 31, 2022
by
iamsubhrajit
134
views
co-and-architecture
cache-memory
2
votes
0
answers
3
cache miss question
In $T_{Read Avg}$, shouldn’t it be $T_{Read Avg}$ = (10*0.9) + 0.1*(10+100), because it must be checking the cache in case of cache miss too, right?
h4kr
asked
in
CO and Architecture
Dec 27, 2022
by
h4kr
112
views
co-and-architecture
cache-memory
multilevel-cache
0
votes
1
answer
4
cache memory
Consider a RISC processor with an ideal CPI, where 25% of the total instructions are LOAD and STORE instruction. Time to accessing main memory is 100 clock cycles and accessing of the cache memory required 2 clock cycles. If cache miss rate is 2%, then the effective CPI for the system with the cache is ____.
someshawasthi
asked
in
CO and Architecture
Nov 17, 2022
by
someshawasthi
131
views
cache-memory
clock-cycles
0
votes
0
answers
5
cache memory
Consider a process where each instruction takes on average 3 cycle and there are 1.8 references to memory per instruction. A program with 50000 instruction is executed on this machine using a split cache of 32KB, obtained a 85% bit rate, 3ns bit time and 21ns miss penalty the execution time for the cache is ___ (μsec)
someshawasthi
asked
in
CO and Architecture
Nov 16, 2022
by
someshawasthi
118
views
co-and-architecture
cache-memory
1
vote
1
answer
6
Zeal test series
A computer system uses $16-$bit memory addresses.It has a $16KB$ cache organized in a $4-$ way set associative manner with $64 $ bytes per cache block.Assume that size of each memory word is 2B .When a program is executed ,The processor read ... .All the above addresses shown in decimal values.Assume cache is initially empty .The number of addresses hit in the cache ?
Kabir5454
asked
in
CO and Architecture
Nov 1, 2022
by
Kabir5454
212
views
zeal
cache-memory
numerical-answers
test-series
1
vote
1
answer
7
cache memory
THE size of memory required at cache controller to store the metadata is 2kbyte The metadata include tag bits 1 modified bit and 1 valid bit The cache contain 1KBlocks of 32 bytes each organized as directed mapped The size of Main memory is __ Mbytes?
Vaishnavi Gadhe
asked
in
CO and Architecture
Oct 25, 2022
by
Vaishnavi Gadhe
192
views
cache-memory
numerical-answers
2
votes
0
answers
8
Operating System: Self Doubt - Memory Management
Considering a system with Single-Level page table, with a TLB to reduce the access time of pages. A cache is also provided with the main memory. All the pages ultimately reside in MM. (assuming there's no page fault). Let, TLB Hit Ratio = x TLB Access ... for TLB miss it will be (a+c+p). But if this is true, why can't we store Page Table in a Cache?
DebRC
asked
in
Operating System
Sep 14, 2022
by
DebRC
165
views
memory-management
operating-system
paging
cache-memory
self-doubt
Page:
1
2
3
4
5
6
...
24
next »
Subscribe to GATE CSE 2023 Test Series
Subscribe to GO Classes for GATE CSE 2023
Quick search syntax
tags
tag:apple
author
user:martin
title
title:apple
content
content:apple
exclude
-tag:apple
force match
+apple
views
views:100
score
score:10
answers
answers:2
is accepted
isaccepted:true
is closed
isclosed:true
Recent Posts
BITSHD 2023
My journey from being a MSc student to AIR 239 in GATE CSE 2023 and qualified UGC-NET JRF.
NEEPCO Recruitment 2023
GATE CSE 2023 Results
IIIT Banglore MTech 2023-24
Subjects
All categories
General Aptitude
(2.5k)
Engineering Mathematics
(9.3k)
Digital Logic
(3.3k)
Programming and DS
(5.9k)
Algorithms
(4.6k)
Theory of Computation
(6.7k)
Compiler Design
(2.3k)
Operating System
(5.0k)
Databases
(4.6k)
CO and Architecture
(3.8k)
Computer Networks
(4.7k)
Non GATE
(1.3k)
Others
(2.5k)
Admissions
(653)
Exam Queries
(845)
Tier 1 Placement Questions
(17)
Job Queries
(76)
Projects
(9)
Unknown Category
(866)
Recent questions tagged cache-memory
Recent Blog Comments
Please provide some tips about NET, since I want...
Amazing story to hear
Link added now:...
Sir can you please provide some good resources...
Where can we see the responses of the form filled?