Recent questions tagged cache-memory

Recent questions tagged cache-memory

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1

Made Easy Test Series
Consider a fully associative cache with 6 cache blocks (0 to 5) and the following sequence of memory block requests: 5, 4, 29, 18, 21, 7, 25, 18, 16, 35, 45, 22, 7, 19 If LRU replacement policy is used, which cache block is used for memory block 19? Assume initially 6 blocks are placed in a cache according to lexicographic order of cache index.

LRU asked in CO and Architecture 3 days ago

by LRU

46 views

2 votes

2 answers

2

Made Easy Test Series
Consider the following statements: S1 : Direct mapped caches do not need a cache block replacement policy, whereas fully associative cache need. S2 : Direct mapped cache, may produce more misses if programs refers to memory words that occupy a same tag value. Which of the following options is correct?

LRU asked in CO and Architecture 3 days ago

by LRU

64 views

1 vote

0 answers

3

Applied Test Series
Consider a memory system that uses a 32-bit address to address at the byte level, plus a cache that uses a 64-byte line size. Assume a four-way set-associative cache with a tag field in the address of 9 bits. The total number of cache lines/ blocks in the cache are_____

LRU asked in CO and Architecture Jan 14

by LRU

51 views

0 votes

1 answer

4

Testbook test series
Can anyone please solve this?

adad20 asked in CO and Architecture Jan 14

by adad20

66 views

1 vote

1 answer

5

APPLIED ROOTS Multisubject test
Consider a 32-bit microprocessor that has an on-chip 16-KByte four-way set-associative cache. Assume that the cache has a line size of four 32-bit words.Where in the cache (Set number in decimal) is the word from memory location ABCDE888 mapped?

samir757 asked in CO and Architecture Dec 23, 2021

80 views

1 vote

1 answer

6

NPTEL Assignment
Consider a direct-mapped cache with 64 blocks and a block size of 16 bytes. Byte address 1200 will map to block number ………… of the cache.

LRU asked in CO and Architecture Dec 4, 2021

by LRU

100 views

0 votes

1 answer

7

Applied Test Series
The cache takes 2 cycles to access and has a 5% miss rate, main memory takes 100 cycles to access and has an 8% miss rate, and the disk takes 10,000 cycles to access. The average memory access time for a given system is____ (in cycles)

LRU asked in CO and Architecture Dec 4, 2021

by LRU

76 views

1 vote

1 answer

8

Applied Test Series
A cache memory system with capacity of N words and block size of B words is to be designed. If it is designed as a direct mapped cache, the length of the TAG field is 14 bits. If it is designed as a 4-way set associative cache, the length of the TAG field will be ………… bits.

LRU asked in CO and Architecture Dec 4, 2021

by LRU

74 views

1 vote

1 answer

9

Applied Test Series
Consider a machine with a byte addressable main memory of 216 bytes and block size of 8 bytes. Assume that a 2-way associative cache consisting of 32 lines is used with this machine. A 16-bit memory address divided into tag, set number, and byte ... sequence of addresses the number of misses are____ 0001 0001 0001 1011 1100 0011 0011 0100 1101 0000 0001 1101 1010 1010 1010 1010

LRU asked in CO and Architecture Dec 4, 2021

by LRU

80 views

2 votes

2 answers

10

Applied Test Series
Consider the following memories with their miss rates and hit times Then the average memory access time is ______ (in ns)

LRU asked in CO and Architecture Nov 5, 2021

by LRU

169 views

3 votes

1 answer

11

Applied Test Series
Consider a memory system that uses a 32-bit address to address at the byte level, plus a cache that uses a 64-byte line size. Assume a four-way set-associative cache with a tag field in the address of 9 bits. The total number of cache lines/ blocks in the cache are_____

LRU asked in CO and Architecture Oct 8, 2021

by LRU

142 views

6 votes

4 answers

12

GATE CSE 2021 Set 2 | Question: 19
Consider a set-associative cache of size $\text{2KB (1KB} =2^{10}$ bytes$\text{)}$ with cache block size of $64$ bytes. Assume that the cache is byte-addressable and a $32$ -bit address is used for accessing the cache. If the width of the tag field is $22$ bits, the associativity of the cache is _________

Arjun asked in CO and Architecture Feb 18, 2021

by Arjun

2.4k views

7 votes

2 answers

13

GATE CSE 2021 Set 2 | Question: 27
Assume a two-level inclusive cache hierarchy, $L1$ and $L2$, where $L2$ is the larger of the two. Consider the following statements. $S_1$: Read misses in a write through $L1$ cache do not result in writebacks of dirty lines to the $L2$ $S_2$: Write ... false $S_1$ is false and $S_2$ is true $S_1$ is true and $S_2$ is true $S_1$ is false and $S_2$ is false

Arjun asked in CO and Architecture Feb 18, 2021

by Arjun

2.6k views

0 votes

4 answers

14

GATE CSE 2021 Set 1 | Question: 22
Consider a computer system with a byte-addressable primary memory of size $2^{32}$ bytes. Assume the computer system has a direct-mapped cache of size $\text{32 KB}$ ($\text{1 KB}$ = $2^{10}$ bytes), and each cache block is of size $64$ bytes. The size of the tag field is __________ bits.

Arjun asked in CO and Architecture Feb 18, 2021

by Arjun

1.7k views

1 vote

1 answer

15

UGCNET-Oct2020-II: 5
Consider a machine with a byte addressable main memory of $2^{16}$ bytes block size of $8$ bytes. Assume that a direct mapped cache consisting of $32$ lines used with this machine. How many bits will be there in Tag, line and word field of format of main memory addresses? $8,5,3$ $8,6,2$ $7,5,4$ $7,6,3$

jothee asked in CO and Architecture Nov 20, 2020

by jothee

1.3k views

0 votes

0 answers

16

NIELIT 2017 OCT Scientific Assistant A (IT) - Section B: 22
In time division switches if each memory access takes $100\;ns $ and one frame period is $125\;\mu s,$ then the maximum number of lines that can be supported is $625$ lines $1250$ lines $2300$ lines $318$ lines

Lakshman Patel RJIT asked in CO and Architecture Apr 1, 2020

by Lakshman Patel RJIT

761 views

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