Recent questions tagged cache-memory

Recent questions tagged cache-memory

4 votes

1 answer

1

GATE CSE 2022 | Question: 14
Let $\text{WB}$ and $\text{WT}$ be two set associative cache organizations that use $\text{LRU}$ algorithm for cache block replacement. $\text{WB}$ is a write back cache and $\text{WT}$ ... cache to main memory. A read miss in $\text{WB}$ will never lead to eviction of a dirty block from $\text{WB}.$

Arjun asked in CO and Architecture Feb 15

by Arjun

1.4k views

3 votes

2 answers

2

GATE CSE 2022 | Question: 23
A cache memory that has a hit rate of $0.8$ has an access latency $10 \; \text{ns}$ and miss penalty $100 \; \text{ns}.$ An optimization is done on the cache to reduce the miss rate. However, the optimization results ... (rounded off to two decimal places) needed after the optimization such that it should not increase the average memory access time is _______________.

Arjun asked in CO and Architecture Feb 15

by Arjun

1.6k views

1 vote

0 answers

3

Made Easy Test Series
Consider a fully associative cache with 6 cache blocks (0 to 5) and the following sequence of memory block requests: 5, 4, 29, 18, 21, 7, 25, 18, 16, 35, 45, 22, 7, 19 If LRU replacement policy is used, which cache block is used for memory block 19? Assume initially 6 blocks are placed in a cache according to lexicographic order of cache index.

LRU asked in CO and Architecture Jan 20

by LRU

171 views

4 votes

3 answers

4

Made Easy Test Series
Consider the following statements: S1 : Direct mapped caches do not need a cache block replacement policy, whereas fully associative cache need. S2 : Direct mapped cache, may produce more misses if programs refers to memory words that occupy a same tag value. Which of the following options is correct?

LRU asked in CO and Architecture Jan 20

by LRU

262 views

1 vote

2 answers

5

Appllied Gate Test Series
A hierarchical memory system that uses cache memory has cache access time of 80 nanoseconds, main memory access time of 200 nanoseconds, 85% of memory requests are for read, hit ratio of 0.9 for read access and the write-through scheme is used. What will be the average access time of the system both for read and write requests ?

Sagar475 asked in CO and Architecture Jan 16

139 views

1 vote

0 answers

6

Applied Test Series
Consider a memory system that uses a 32-bit address to address at the byte level, plus a cache that uses a 64-byte line size. Assume a four-way set-associative cache with a tag field in the address of 9 bits. The total number of cache lines/ blocks in the cache are_____

LRU asked in CO and Architecture Jan 14

by LRU

174 views

0 votes

1 answer

7

Testbook test series
Can anyone please solve this?

Aditya_ asked in CO and Architecture Jan 14

156 views

1 vote

1 answer

8

APPLIED ROOTS Multisubject test
Consider a 32-bit microprocessor that has an on-chip 16-KByte four-way set-associative cache. Assume that the cache has a line size of four 32-bit words.Where in the cache (Set number in decimal) is the word from memory location ABCDE888 mapped?

samir757 asked in CO and Architecture Dec 23, 2021

165 views

0 votes

2 answers

9

Testbook Test Series
In designing a computer’s cache system,

rsansiya111 asked in CO and Architecture Dec 23, 2021

115 views

1 vote

1 answer

10

NPTEL Assignment
Consider a direct-mapped cache with 64 blocks and a block size of 16 bytes. Byte address 1200 will map to block number ………… of the cache.

LRU asked in CO and Architecture Dec 4, 2021

by LRU

190 views

0 votes

1 answer

11

Applied Test Series
The cache takes 2 cycles to access and has a 5% miss rate, main memory takes 100 cycles to access and has an 8% miss rate, and the disk takes 10,000 cycles to access. The average memory access time for a given system is____ (in cycles)

LRU asked in CO and Architecture Dec 4, 2021

by LRU

146 views

1 vote

1 answer

12

Applied Test Series
A cache memory system with capacity of N words and block size of B words is to be designed. If it is designed as a direct mapped cache, the length of the TAG field is 14 bits. If it is designed as a 4-way set associative cache, the length of the TAG field will be ………… bits.

LRU asked in CO and Architecture Dec 4, 2021

by LRU

141 views

1 vote

1 answer

13

Applied Test Series
Consider a machine with a byte addressable main memory of 216 bytes and block size of 8 bytes. Assume that a 2-way associative cache consisting of 32 lines is used with this machine. A 16-bit memory address divided into tag, set number, and byte ... sequence of addresses the number of misses are____ 0001 0001 0001 1011 1100 0011 0011 0100 1101 0000 0001 1101 1010 1010 1010 1010

LRU asked in CO and Architecture Dec 4, 2021

by LRU

223 views

2 votes

2 answers

14

Applied Test Series
Consider the following memories with their miss rates and hit times Then the average memory access time is ______ (in ns)

LRU asked in CO and Architecture Nov 5, 2021

by LRU

237 views

3 votes

1 answer

15

Applied Test Series
Consider a memory system that uses a 32-bit address to address at the byte level, plus a cache that uses a 64-byte line size. Assume a four-way set-associative cache with a tag field in the address of 9 bits. The total number of cache lines/ blocks in the cache are_____

LRU asked in CO and Architecture Oct 8, 2021

by LRU

188 views

8 votes

4 answers

16

GATE CSE 2021 Set 2 | Question: 19
Consider a set-associative cache of size $\text{2KB (1KB} =2^{10}$ bytes$\text{)}$ with cache block size of $64$ bytes. Assume that the cache is byte-addressable and a $32$ -bit address is used for accessing the cache. If the width of the tag field is $22$ bits, the associativity of the cache is _________

Arjun asked in CO and Architecture Feb 18, 2021

by Arjun

3.0k views

9 votes

2 answers

17

GATE CSE 2021 Set 2 | Question: 27
Assume a two-level inclusive cache hierarchy, $L1$ and $L2$, where $L2$ is the larger of the two. Consider the following statements. $S_1$: Read misses in a write through $L1$ cache do not result in writebacks of dirty lines to the $L2$ $S_2$: Write ... false $S_1$ is false and $S_2$ is true $S_1$ is true and $S_2$ is true $S_1$ is false and $S_2$ is false

Arjun asked in CO and Architecture Feb 18, 2021

by Arjun

3.4k views

1 vote

4 answers

18

GATE CSE 2021 Set 1 | Question: 22
Consider a computer system with a byte-addressable primary memory of size $2^{32}$ bytes. Assume the computer system has a direct-mapped cache of size $\text{32 KB}$ ($\text{1 KB}$ = $2^{10}$ bytes), and each cache block is of size $64$ bytes. The size of the tag field is __________ bits.

Arjun asked in CO and Architecture Feb 18, 2021

by Arjun

2.4k views

1 vote

1 answer

19

UGC NET CSE | October 2020 | Part 2 | Question: 5
Consider a machine with a byte addressable main memory of $2^{16}$ bytes block size of $8$ bytes. Assume that a direct mapped cache consisting of $32$ lines used with this machine. How many bits will be there in Tag, line and word field of format of main memory addresses? $8,5,3$ $8,6,2$ $7,5,4$ $7,6,3$

go_editor asked in CO and Architecture Nov 20, 2020

1.7k views

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