search
Log In

Recent questions tagged cache-memory

4 votes
3 answers
1
Consider a set-associative cache of size $\text{2KB (1KB} =2^{10}$ bytes$\text{)}$ with cache block size of $64$ bytes. Assume that the cache is byte-addressable and a $32$ -bit address is used for accessing the cache. If the width of the tag field is $22$ bits, the associativity of the cache is _________
asked Feb 18 in CO and Architecture Arjun 996 views
1 vote
2 answers
2
Assume a two-level inclusive cache hierarchy, $L1$ and $L2$, where $L2$ is the larger of the two. Consider the following statements. $S_1$: Read misses in a write through $L1$ cache do not result in writebacks of dirty lines to the $L2$ $S_2$: Write allocate policy must be ... $S_2$ is false $S_1$ is false and $S_2$ is true $S_1$ is true and $S_2$ is true $S_1$ is false and $S_2$ is false
asked Feb 18 in CO and Architecture Arjun 772 views
0 votes
3 answers
3
Consider a computer system with a byte-addressable primary memory of size $2^{32}$ bytes. Assume the computer system has a direct-mapped cache of size $\text{32 KB}$ ($\text{1 KB}$ = $2^{10}$ bytes), and each cache block is of size $64$ bytes. The size of the tag field is __________ bits.
asked Feb 18 in CO and Architecture Arjun 501 views
1 vote
1 answer
4
Consider a machine with a byte addressable main memory of $2^{16}$ bytes block size of $8$ bytes. Assume that a direct mapped cache consisting of $32$ lines used with this machine. How many bits will be there in Tag, line and word field of format of main memory addresses? $8,5,3$ $8,6,2$ $7,5,4$ $7,6,3$
asked Nov 20, 2020 in CO and Architecture jothee 590 views
0 votes
0 answers
5
In time division switches if each memory access takes $100\;ns $ and one frame period is $125\;\mu s,$ then the maximum number of lines that can be supported is $625$ lines $1250$ lines $2300$ lines $318$ lines
asked Apr 1, 2020 in CO and Architecture Lakshman Patel RJIT 498 views
1 vote
3 answers
6
In a particular system it is observed that, the cache performance gets improved as a result of increasing the block size of the cache. The primary reason behind this is : Programs exhibits temporal locality Programs have small working set Read operation is frequently required rather than write operation Programs exhibits spatial locality
asked Mar 31, 2020 in Operating System Lakshman Patel RJIT 484 views
0 votes
3 answers
7
0 votes
4 answers
8
1 vote
4 answers
9
Which of the following is added to the page table in order to track whether a page of cache has been modified since it was read from the memory? Reference bit Dirty bit Tag bit Valid bit
asked Mar 30, 2020 in Operating System Lakshman Patel RJIT 1.1k views
5 votes
5 answers
10
A direct mapped cache memory of $1$ MB has a block size of $256$ bytes. The cache has an access time of $3$ ns and a hit rate of $94 \%$. During a cache miss, it takes $2$0 ns to bring the first word of a block from the main memory, while each subsequent word takes $5$ ns. The word size is $64$ bits. The average memory access time in ns (round off to $1$ decimal place) is______.
asked Feb 12, 2020 in CO and Architecture Arjun 6.9k views
9 votes
3 answers
11
A computer system with a word length of $32$ bits has a $16$ MB byte- addressable main memory and a $64$ KB, $4$-way set associative cache memory with a block size of $256$ ... same cache set. $A3$ and $A4$ are mapped to the same cache set. $A1$ and $A3$ are mapped to the same cache set.
asked Feb 12, 2020 in CO and Architecture Arjun 7.5k views
5 votes
4 answers
12
How many total bits are required for a direct-mapped cache with $128$ KB of data and $1$ word block size, assuming a $32$-bit address and $1$ word size of $4$ bytes? $2$ Mbits $1.7$ Mbits $2.5$ Mbits $1.5$ Mbits
asked Jan 13, 2020 in CO and Architecture Satbir 1.9k views
2 votes
3 answers
13
Which of the following is an efficient method of cache updating? Snoopy writes Write through Write within Buffered write
asked Jan 13, 2020 in CO and Architecture Satbir 1.4k views
0 votes
0 answers
14
The performance of a file system depends upon the cache hit rate (fraction of blocks found in the cache). If it takes $1\: msec$ to satisfy a request from the cache, but $40\: msec$ to satisfy a request if a disk read is needed, give a formula for the mean time required to satisfy a request if the hit rate is $h.$ Plot this function for values of $h$ varying from $0$ to $1.0.$
asked Oct 27, 2019 in Operating System Lakshman Patel RJIT 152 views
0 votes
0 answers
15
0 votes
2 answers
16
To use cache memory, main memory is divided into cache lines, typically $32$ or $64$ bytes long. An entire cache line is cached at once. What is the advantage of caching an entire line instead of a single byte or word at a time?
asked Oct 21, 2019 in Operating System Lakshman Patel RJIT 213 views
...