menu
Login
Register
search
Log In
account_circle
Log In
Email or Username
Password
Remember
Log In
Register
I forgot my password
Register
Username
Email
Password
Register
add
Activity
Questions
Unanswered
Tags
Subjects
Users
Ask
Prev
Blogs
New Blog
Exams
Quick search syntax
tags
tag:apple
author
user:martin
title
title:apple
content
content:apple
exclude
-tag:apple
force match
+apple
views
views:100
score
score:10
answers
answers:2
is accepted
isaccepted:true
is closed
isclosed:true
Recent Posts
Barc Interview Experience 2020- CSE stream
JEST 2021 registrations are open
TIFR GS-2021 Online Application portal
IIT Jodhpur Mtech AI - Interview Expierence (Summer Admission)
Interview experience at IIT Tirupati for MS program winter admission
Subjects
All categories
General Aptitude
(2.1k)
Engineering Mathematics
(8.5k)
Digital Logic
(3k)
Programming and DS
(5.1k)
Algorithms
(4.5k)
Theory of Computation
(6.3k)
Compiler Design
(2.2k)
Operating System
(4.7k)
Databases
(4.3k)
CO and Architecture
(3.5k)
Computer Networks
(4.3k)
Non GATE
(1.2k)
Others
(1.3k)
Admissions
(595)
Exam Queries
(838)
Tier 1 Placement Questions
(16)
Job Queries
(71)
Projects
(19)
Unknown Category
(1.1k)
Recent questions tagged cache-memory
Recent Blog Comments
yeah right!
@atulbrk IISc is mentioned only...
@nephron Please share the link of the PDF of the...
I think The JEST website rercently updated the...
hi this pdf have gate prevoius year questions or...
Network Sites
GO Mechanical
GO Electrical
GO Electronics
GO Civil
CSE Doubts
Slides
A Simple Illustration
Cache Memory
Recent questions tagged cache-memory
1
vote
1
answer
1
UGCNET-Oct2020-II: 5
Consider a machine with a byte addressable main memory of $2^{16}$ bytes block size of $8$ bytes. Assume that a direct mapped cache consisting of $32$ lines used with this machine. How many bits will be there in Tag, line and word field of format of main memory addresses? $8,5,3$ $8,6,2$ $7,5,4$ $7,6,3$
Consider a machine with a byte addressable main memory of $2^{16}$ bytes block size of $8$ bytes. Assume that a direct mapped cache consisting of $32$ lines used with this machine. How many bits will be there in Tag, line and word field of format of main memory addresses? $8,5,3$ $8,6,2$ $7,5,4$ $7,6,3$
asked
Nov 20, 2020
in
CO and Architecture
jothee
205
views
ugcnet-oct2020-ii
co-and-architecture
cache-memory
0
votes
1
answer
2
NIELIT 2017 OCT Scientific Assistant A (IT) - Section B: 22
In time division switches if each memory access takes $100\;ns $ and one frame period is $125\;\mu s,$ then the maximum number of lines that can be supported is $625$ lines $1250$ lines $2300$ lines $318$ lines
In time division switches if each memory access takes $100\;ns $ and one frame period is $125\;\mu s,$ then the maximum number of lines that can be supported is $625$ lines $1250$ lines $2300$ lines $318$ lines
asked
Apr 1, 2020
in
CO and Architecture
Lakshman Patel RJIT
277
views
nielit2017oct-assistanta-it
co-and-architecture
cache-memory
1
vote
2
answers
3
NIELIT 2017 DEC Scientific Assistant A - Section B: 56
In a particular system it is observed that, the cache performance gets improved as a result of increasing the block size of the cache. The primary reason behind this is : Programs exhibits temporal locality Programs have small working set Read operation is frequently required rather than write operation Programs exhibits spatial locality
In a particular system it is observed that, the cache performance gets improved as a result of increasing the block size of the cache. The primary reason behind this is : Programs exhibits temporal locality Programs have small working set Read operation is frequently required rather than write operation Programs exhibits spatial locality
asked
Mar 31, 2020
in
Operating System
Lakshman Patel RJIT
382
views
nielit2017dec-assistanta
operating-system
cache-memory
0
votes
3
answers
4
NIELIT 2016 DEC Scientist B (CS) - Section B: 37
The principle of locality of reference justifies the use of Non reusable Cache memory Virtual memory None of the above
The principle of locality of reference justifies the use of Non reusable Cache memory Virtual memory None of the above
asked
Mar 31, 2020
in
Operating System
Lakshman Patel RJIT
317
views
nielit2016dec-scientistb-cs
operating-system
cache-memory
0
votes
4
answers
5
NIELIT 2017 DEC Scientist B - Section B: 4
In a cache memory if total number of sets are ‘$s$’, then the set offset is: $2^8$ $\log_2s$ $s^2$ $s$
In a cache memory if total number of sets are ‘$s$’, then the set offset is: $2^8$ $\log_2s$ $s^2$ $s$
asked
Mar 30, 2020
in
CO and Architecture
Lakshman Patel RJIT
693
views
nielit2017dec-scientistb
co-and-architecture
cache-memory
0
votes
4
answers
6
NIELIT 2017 DEC Scientist B - Section B: 16
Which of the following is added to the page table in order to track whether a page of cache has been modified since it was read from the memory? Reference bit Dirty bit Tag bit Valid bit
Which of the following is added to the page table in order to track whether a page of cache has been modified since it was read from the memory? Reference bit Dirty bit Tag bit Valid bit
asked
Mar 30, 2020
in
Operating System
Lakshman Patel RJIT
797
views
nielit2017dec-scientistb
operating-system
memory-management
page-table
cache-memory
8
votes
4
answers
7
GATE 2020 CSE | Question: 30
A computer system with a word length of $32$ bits has a $16$ MB byte- addressable main memory and a $64$ KB, $4$-way set associative cache memory with a block size of $256$ ... set. $A3$ and $A4$ are mapped to the same cache set. $A1$ and $A3$ are mapped to the same cache set.
A computer system with a word length of $32$ bits has a $16$ MB byte- addressable main memory and a $64$ KB, $4$-way set associative cache memory with a block size of $256$ bytes. Consider the following four physical addresses represented in hexadecimal notation. $A1= 0x42C8A4$ ... same cache set. $A3$ and $A4$ are mapped to the same cache set. $A1$ and $A3$ are mapped to the same cache set.
asked
Feb 12, 2020
in
CO and Architecture
Arjun
4.5k
views
gate2020-cs
cache-memory
4
votes
2
answers
8
ISRO2020-47
How many total bits are required for a direct-mapped cache with $128$ KB of data and $1$ word block size, assuming a $32$-bit address and $1$ word size of $4$ bytes? $2$ Mbits $1.7$ Mbits $2.5$ Mbits $1.5$ Mbits
How many total bits are required for a direct-mapped cache with $128$ KB of data and $1$ word block size, assuming a $32$-bit address and $1$ word size of $4$ bytes? $2$ Mbits $1.7$ Mbits $2.5$ Mbits $1.5$ Mbits
asked
Jan 13, 2020
in
CO and Architecture
Satbir
1.3k
views
isro-2020
co-and-architecture
cache-memory
direct-mapping
normal
2
votes
3
answers
9
ISRO2020-43
Which of the following is an efficient method of cache updating? Snoopy writes Write through Write within Buffered write
Which of the following is an efficient method of cache updating? Snoopy writes Write through Write within Buffered write
asked
Jan 13, 2020
in
CO and Architecture
Satbir
1.2k
views
isro-2020
co-and-architecture
cache-memory
normal
0
votes
0
answers
10
Andrew S. Tanenbaum (OS) Edition 4 Exercise 4 Question 32 (Page No. 335)
The performance of a file system depends upon the cache hit rate (fraction of blocks found in the cache). If it takes $1\: msec$ to satisfy a request from the cache, but $40\: msec$ to satisfy a request if a disk read is needed ... request if the hit rate is $h.$ Plot this function for values of $h$ varying from $0$ to $1.0.$
The performance of a file system depends upon the cache hit rate (fraction of blocks found in the cache). If it takes $1\: msec$ to satisfy a request from the cache, but $40\: msec$ to satisfy a request if a disk read is needed, give a formula for the mean time required to satisfy a request if the hit rate is $h.$ Plot this function for values of $h$ varying from $0$ to $1.0.$
asked
Oct 27, 2019
in
Operating System
Lakshman Patel RJIT
110
views
tanenbaum
operating-system
file-system
cache-memory
descriptive
0
votes
0
answers
11
Andrew S. Tanenbaum (OS) Edition 4 Exercise 2 Question 10 (Page No. 174)
In the text it was stated that the model of Fig. $2-11(a)$ was not suited to a file server using a cache in memory. Why not? Could each process have its own cache?
In the text it was stated that the model of Fig. $2-11(a)$ was not suited to a file server using a cache in memory. Why not? Could each process have its own cache?
asked
Oct 24, 2019
in
Operating System
Lakshman Patel RJIT
61
views
tanenbaum
operating-system
process-and-threads
cache-memory
descriptive
0
votes
2
answers
12
Andrew S. Tanenbaum (OS) Edition 4 Exercise 1 Question 4 (Page No. 81)
To use cache memory, main memory is divided into cache lines, typically $32$ or $64$ bytes long. An entire cache line is cached at once. What is the advantage of caching an entire line instead of a single byte or word at a time?
To use cache memory, main memory is divided into cache lines, typically $32$ or $64$ bytes long. An entire cache line is cached at once. What is the advantage of caching an entire line instead of a single byte or word at a time?
asked
Oct 21, 2019
in
Operating System
Lakshman Patel RJIT
152
views
tanenbaum
operating-system
introduction
cache-memory
descriptive
1
vote
0
answers
13
Caching
Given the following information: TLB hit rate 95%, TLB access time is 1 cycle. cache hit rate 90 %, cache access time is 1 cycle. When TLB and cache both get miss; page fault rate is 1% The TLB access and acache access are ... cycles Access to hard drive requires 50,000 cycles. Compute the average memory access latencies when the cache is physically addresses (in cycles).
Given the following information: TLB hit rate 95%, TLB access time is 1 cycle. cache hit rate 90 %, cache access time is 1 cycle. When TLB and cache both get miss; page fault rate is 1% The TLB access and acache access are sequential. ... 75 cycles Access to hard drive requires 50,000 cycles. Compute the average memory access latencies when the cache is physically addresses (in cycles).
asked
Mar 10, 2019
in
CO and Architecture
s_dr_13
405
views
cache-memory
co-and-architecture
virtual-memory
tlb
0
votes
1
answer
14
Self doubt(Hamacher and Zaky)
Memory is word addressable with 16 bit addresses Word size=16 bits Each block is of size 16 bits. The cache contains 8 blocks. What is the address division for: 1>direct. 2>associative 3>set associative cache
Memory is word addressable with 16 bit addresses Word size=16 bits Each block is of size 16 bits. The cache contains 8 blocks. What is the address division for: 1>direct. 2>associative 3>set associative cache
asked
Feb 17, 2019
in
CO and Architecture
DIYA BASU
227
views
cache-memory
15
votes
7
answers
15
GATE2019-1
A certain processor uses a fully associative cache of size $16$ kB, The cache block size is $16$ bytes. Assume that the main memory is byte addressable and uses a $32$-bit address. How many bits are required for the Tag and the Index fields respectively in the addresses generated by the processor? $24$ bits and $0$ bits $28$ bits and $4$ bits $24$ bits and $4$ bits $28$ bits and $0$ bits
A certain processor uses a fully associative cache of size $16$ kB, The cache block size is $16$ bytes. Assume that the main memory is byte addressable and uses a $32$-bit address. How many bits are required for the Tag and the Index fields respectively in the addresses generated by the processor? $24$ bits and $0$ bits $28$ bits and $4$ bits $24$ bits and $4$ bits $28$ bits and $0$ bits
asked
Feb 7, 2019
in
CO and Architecture
Arjun
9.1k
views
gate2019
co-and-architecture
cache-memory
normal
30
votes
9
answers
16
GATE2019-45
A certain processor deploys a single-level cache. The cache block size is $8$ words and the word size is $4$ bytes. The memory system uses a $60$-MHz clock. To service a cache miss, the memory controller first takes $1$ cycle to accept the ... bandwidth for the memory system when the program running on the processor issues a series of read operations is ______$\times 10^6$ bytes/sec
A certain processor deploys a single-level cache. The cache block size is $8$ words and the word size is $4$ bytes. The memory system uses a $60$-MHz clock. To service a cache miss, the memory controller first takes $1$ cycle to accept the starting ... bandwidth for the memory system when the program running on the processor issues a series of read operations is ______$\times 10^6$ bytes/sec
asked
Feb 7, 2019
in
CO and Architecture
Arjun
8.3k
views
gate2019
numerical-answers
co-and-architecture
cache-memory
2
votes
0
answers
17
ME adv mock
A hypothetical processor on cache read miss requires one clock to send an address to Main Memory (MM) and eight clock cycles to access a 64-bit word from MM to processor cache. Miss rate of read is decreased from 14.8% to 2.6% when line size ... words. The speed up of processor is achieved in dealing with average read miss after increasing the line size is_____ (Upto 2 decimal places)
A hypothetical processor on cache read miss requires one clock to send an address to Main Memory (MM) and eight clock cycles to access a 64-bit word from MM to processor cache. Miss rate of read is decreased from 14.8% to 2.6% when line size of cache ... words. The speed up of processor is achieved in dealing with average read miss after increasing the line size is_____ (Upto 2 decimal places)
asked
Feb 1, 2019
in
CO and Architecture
newdreamz a1-z0
243
views
co-and-architecture
cache-memory
0
votes
1
answer
18
GRADEUP
For a 4 bit set associative cache 10 bits are required as index to specify cache block. The main memory is of size 4G x 32. Size of cache memory is? Answer is 4096*49. Please explain the notation also.
For a 4 bit set associative cache 10 bits are required as index to specify cache block. The main memory is of size 4G x 32. Size of cache memory is? Answer is 4096*49. Please explain the notation also.
asked
Feb 1, 2019
in
CO and Architecture
Aman Janko
218
views
co-and-architecture
cache-memory
0
votes
1
answer
19
computer organization
Consider the hypothetical processor is supports both 2 address and one address instructions. It has 128-word memory A 16-bit instruction is placed in the one memory word. Q1.What is the range of two address and one address instructions are supported? A)1 to ... instructions can be supported? A)128 B)2 C)256 D)32 PLEASE GIVE SOLUTION IN DETAILED MANNER...ESPECIALLY FOR PART 1.
Consider the hypothetical processor is supports both 2 address and one address instructions. It has 128-word memory A 16-bit instruction is placed in the one memory word. Q1.What is the range of two address and one address instructions are supported? A)1 to 3 and 128 ... address instructions can be supported? A)128 B)2 C)256 D)32 PLEASE GIVE SOLUTION IN DETAILED MANNER...ESPECIALLY FOR PART 1.
asked
Feb 1, 2019
in
CO and Architecture
learner_geek
1.1k
views
co-and-architecture
cache-memory
machine-instructions
instruction-format
computer-architecture
Page:
1
2
3
4
5
6
...
18
next »
...