Recent questions tagged cache-memory

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1

Computer system organization cache memory
Assume that A, B , and C are memory addresses each of which are in different block of memory. Further assume A, B , C are generated in a uniformly random way. What is the probability that the second instance of "B" will be a hit on a 4-line direct-mapped cache?

asked 1 day ago in CO & Architecture by Nikita Shadija (7 points) | 12 views

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2

made easy cbt-1 2019
consider a computer with 4 GB main memory synchronized with CPU speed using 8-way set associative cache of 16 KB. memory system is organized into 64 word blocks and word length of CPU is 64 bits. the size of tag in cache line in the set is ______ bits. (answer is 21)

asked 2 days ago in Operating System by Satbir Active (3k points) | 89 views

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3

Self doubt about LRU and Direct mapping cache
Can we apply LRU policy to direct mapped cache. according to me it doesn't make any sense as eventually it will be like FIFO only as unique memory addresses are assigned to each cache line. But my doubt / confusion is can we implement LRU on direct mapped caches?

asked 5 days ago in CO & Architecture by S Ram Active (1.9k points) | 10 views

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4

VIRTUAL GATE TEST SERIES

asked 6 days ago in CO & Architecture by Ajay Maurya 6 (91 points) | 22 views

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5

GATE 2019 2-way set associative
plz explain …..??

asked Jan 7 in Operating System by Vikas123 (355 points) | 31 views

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ME_test_series
A CPU has recorded 450 memory references. The CPU has been organized into 2-level of cache memory L1 and L2 . There are 50 misses and 25 misses in L1 and L2 respectively. The miss penalty from L2 cache to memory is 60 cycles and hit time of L2 cache is 30 cycles. What is the average stall (in cycles) per instruction.? 20 40 80 32

asked Jan 7 in CO & Architecture by Shivam Kasat Active (1.6k points) | 43 views

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7

MADEEASY- CO - SET Associative mapping
Assume a new cache design is proposed by a student. But he later discovered design has too many conflict misses and to resolve this issue he increases the associativity in the design. Which of the following implication will occur in the ... bit increases C. No implications in the design what does INDEX bits refers to in set associative and associative mapping?

asked Dec 29, 2018 in CO & Architecture by Markzuck (393 points) | 53 views

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ME_test_series
Consider the following statements: S1: Direct mapped caches do not need a cache block replacement policy, where as fully associative cache need. S2:: Direct mapped cache, may produce more misses if programs refers to memory words that occupy a same tag value. Which of the following options is correct? How S1 is true?

asked Dec 28, 2018 in CO & Architecture by Shivam Kasat Active (1.6k points) | 41 views

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9

GO2019-FLT1-41
Consider a Computer system with a single core CPU, a single level of cache of size $4 \text{MB}$, and main memory. It takes one CPU cycle to access a memory byte if it is in cache, and $145$ cycles if the memory access incurs a cache miss and must be fetched from main memory. The ... of $A$ and $B$ is read in sequence as follows: for (i=0;i<N;i++) { read A[i]; read B{i]; }

asked Dec 27, 2018 in CO & Architecture by Ruturaj Mohanty Active (1.8k points) | 169 views

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test series
The cache can hold 64 KB .data is transferred between main memory and cache in blocks of 4 bytes each.the main memory consist of 16 M Bytes . if the cache memory is 16-way set associative,Then the hexa decimal main memory address AAAAAA is mapped into which cache set?

asked Dec 27, 2018 in CO & Architecture by Amar Khade (25 points) | 47 views

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11

Miss Penalty
Suppose there are $2$ level cache. If there are $L_{1}$ and $L_{2}$ are $2$ level cache, if both have some miss rate, then still why we need miss penalty for cache in both levels?

asked Dec 27, 2018 in CO & Architecture by srestha Veteran (106k points) | 54 views

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12

ME TEST
Consider Prof. Vamshi s writes a program given below and run on system which has 2-way set associative 16 KB data cache with 32 bytes block where each word size is 32 bits and LRU replacement policy used. If base address of array 'a is 0x0 and initially cache ... i] + a[1024* i]; what will be the physical memory size here?and how many bits should we assign for physical memory addressing?

asked Dec 25, 2018 in CO & Architecture by newdreamz a1-z0 Active (1k points) | 48 views

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13

Calculating memory traffic in caching
Consider a cache with a line size of 64 bytes. Assume that on average 30% of the lines in the cache are dirty. A word consists of 8 bytes. Assume there is a 3% miss rate (0.97 hit ratio). Compute the amount of main memory traffic, in ... is read into cache one line at a time. However, for write back, a single word can be written from cache to main memory.

asked Dec 24, 2018 in CO & Architecture by Raj Singh 1 (207 points) | 41 views

+1 vote

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14

Average memory stall
Consider a CPU contains 2000 instructions, there are 80 misses in L1 cache and 40 misses in the L2 cache. Assume miss penalty from the L2 cache to memory is 200 clock cycles, the hit time of L2 cache is 30 clock cycles, the hit ... .8 memory references per instruction, then average stall per instruction is ________. Can you please suggest the method to attempt such questions.

asked Dec 22, 2018 in CO & Architecture by Shamim Ahmed Active (2.1k points) | 68 views

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2 answers

15

Memory Heirarchy Doubt
Consider a single level cache with an access time of 2.5ns with a block size of 64 bytes. Main Memory uses a block transfer capability that has a first word (4 bytes) access time of 50ns and an access time of 5ns for each word ... to consider a Strict memory hierarchy method or Parallel accessing method in Solving these types of questions? By Default which way is followed?

asked Dec 22, 2018 in CO & Architecture by Ashwani Yadav Junior (861 points) | 66 views

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1 answer

16

Determine Access time of system
If Cache access time is 10 ns . main memory access time is 150 ns. Cache hit rate is 99%. Determine effective access time of system.

asked Dec 21, 2018 in CO & Architecture by Alina (27 points) | 42 views

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17

Direct Mapping
what’s the answer here ...unable to understand their solution. and also shouldn’t be the reason like this For R to be true: “ A unique cache page is associated with every main memory page in direct mapped caches. “

asked Dec 20, 2018 in CO & Architecture by Ashwani Yadav Junior (861 points) | 49 views

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18

Calculating average access time in multi level cache
$h_1→L1$ hit ratio $h_2→L2$ hit ratio $C_1→ L1$ access time $C_2→ $Miss penalty to transfer information from L2 to L1 $M→$ Miss penalty to transfer information from main memory to L2 Average access time given in Carl Hamacher's book is ... red. Is my equation correct or book's equation. Or something more is going on here, which I am unaware of?

asked Dec 19, 2018 in CO & Architecture by Raj Singh 1 (207 points) | 58 views

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19

Calculating cache penalty
For a system with two levels of cache, define $T_{c1}$ first-level cache access time; $T_{c2}$ second-level cache access time; $T_m$ memory access time; $H_1$ first-level cache hit ratio; $H_2$ combined first/second level cache hit ratio. Provide an equation for effective access time $T_a$ for a read operation.

asked Dec 19, 2018 in CO & Architecture by Raj Singh 1 (207 points) | 28 views

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20

Direct Mapping and set associative Mapping
https://gateoverflow.in/1851/gate2006-74 https://gateoverflow.in/43565/gate2006-75 can someone check this questions ? i am not getting, how without help of MULTIPLEXER or DECODER, we are searching hit/miss i mean in direct mapping, how we select lines and their respective Tags without help of Multiplexer ?

asked Dec 18, 2018 in CO & Architecture by Shaik Masthan Veteran (50.1k points) | 208 views

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21

Set associative cache implementation
Given the following specifications for an external cache memory: four-way set associative; line size of two 16-bit words; able to accommodate a total of 4K 32-bit words from main memory; used with a 16-bit processor that issues 24-bit addresses. Show how cache interprets the processor’s addresses.

asked Dec 18, 2018 in CO & Architecture by Raj Singh 1 (207 points) | 33 views

+1 vote

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22

METest_COA
Consider professor vamshi writes a program given below and run on a system which has 2way set associative 16KB data cache with 32 bytes block where each word size is 32 bits and LRU replacement policy is used. and the base address of the array is $0x0$ and ... new block is accessed which causes a cache miss. Total misses=$1023+128=1151$ Please let me know If I went somewhere wrong.

asked Dec 12, 2018 in CO & Architecture by Ayush Upadhyaya Boss (22.7k points) | 50 views

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23

https://gateoverflow.in/14480/formula-write-back-write-through-access-time-parallel-serial

asked Dec 12, 2018 in CO & Architecture by sushmita Boss (16.5k points) | 58 views

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24

General doubt.
I am unable to understand the memory access time for hierarchical and simultaneous access using write back policy even after reading from go sources. Can someone plz explain?

asked Dec 12, 2018 in CO & Architecture by sushmita Boss (16.5k points) | 21 views

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25

conceptual doubt
in case of hierarchical memory organization when there is a miss in cache , we need to bring the entire block from main memory to cache so in the formula- AMAT= H1*T1+(1-H1(T1+T2)) T1- cache access time/word T2= memory access time/word T2 ... in some cases we just take word access time of main memory. also please tell me what should be T2 in case of simultaneous organization?

asked Dec 12, 2018 in CO & Architecture by sushmita Boss (16.5k points) | 29 views

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26

COA: Cache Memory
Consider a 16-way set associative cache which holds 64 KB of data. The size of physical address is 40 bits. A cache block consist of 4 words. Every data word is of 32 bits. Assuming that all cache entries are initially empty and data words are word-addressable. How many bits are required ... =$ 2^{12}/2^2 = 2^{10}$ Word offset $= 2 bits$ Set Offsets $= 10 bits$ Tag bits $= 28$

asked Dec 11, 2018 in CO & Architecture by chauhansunil20th Active (3.9k points) | 52 views

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27

Stallings (write through)
Consider a cache with a line size of 32 bytes and a main memory that requires 30 ns to transfer a 4-byte word. For any line that is written at least once before being swapped out of the cache, what is the average number of times that the line must be written before being swapped out for a write-back cache to be more efficient that a write-through cache?

asked Dec 11, 2018 in CO & Architecture by Ajit J (421 points) | 29 views

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28

Hamacher

asked Dec 8, 2018 in CO & Architecture by aditi19 Active (2.2k points) | 30 views

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1 answer

29

GA Test Series
answer is 1.. but I’m getting more than 1

asked Dec 6, 2018 in CO & Architecture by aditi19 Active (2.2k points) | 47 views

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30

GA Testseries

asked Dec 6, 2018 in CO & Architecture by aditi19 Active (2.2k points) | 50 views

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