Recent questions tagged cache-memory

+1 vote

2 answers

1

Set way Associative

asked 3 days ago in CO & Architecture by Na462 Loyal (6.9k points) | 36 views

+1 vote

0 answers

2

COA: Cache Accesss Time
Little confusion with these questions. What will be o/p for these two questions one with Write back and the other is Write through. 1.)A 128 word cache and main memory are divided into 8 word blocks. The access time of a cache ... average access time? What will be the default technique ( write-allocate and no write-allocate)followed for Hierarchal and Simultaneous access ?

asked Nov 7 in CO & Architecture by Hemanth_13 Active (3k points) | 38 views

0 votes

1 answer

3

Cache Memory
More than one word is put in one cache block to (a) Exploit temporal locality references in a program (b) Exploit spatial locality references in a program (c) Reduce miss penalty (d) All of these

asked Nov 2 in CO & Architecture by Dhiraj Raj (79 points) | 25 views

0 votes

0 answers

4

COA: Cache Average Access Time
A 128 word cache and main memory are divided into 8 word blocks. The access time of a cache and main memory are 10ns/word and 25ns/word respectively. The hit ratio for read operation is 90% and writes operation is 80%. Let there are 60% references for read operations, using write through. What is the average access time? a) 10 ns b) 17 ns c) 19 ns d) 20 ns

asked Oct 25 in CO & Architecture by chauhansunil20th Junior (791 points) | 103 views

+2 votes

0 answers

5

No of cache misses

asked Oct 12 in CO & Architecture by Shubhanshu Boss (16.2k points) | 76 views

0 votes

1 answer

6

Made easy test sesries 2019: COA 2
Consider a direct mapped cache with 16 block with block size of 16 bytes. Initially the cache is empty. The following sequence of access of memory block: 0x80000, 0x80008, 0x80010, 0x80018, 0x30010 is repeated 10 times. Which of the following represents number of ... = 18 B) compulsory = 3 and conflict = 18 C) compulsory = 3 and conflict = 16 D) None of these

asked Oct 2 in CO & Architecture by JAYKISHAN (25 points) | 58 views

+2 votes

2 answers

7

Cache Mapping

asked Oct 1 in CO & Architecture by Na462 Loyal (6.9k points) | 61 views

0 votes

0 answers

8

Self-doubt What events happen in Cache Access duration

asked Sep 29 in CO & Architecture by Harsh Kumar Junior (803 points) | 30 views

0 votes

0 answers

9

Self-doubt Cache Access Time theory
What events happen when we say that a cache at level i is accessed. My understanding is the following events occur in the duration of an access time: The level i cache memory's RAM is accessed using the data bus. The cache RAM loads the required ... access duration? Do we include any extra time for STORING the data in the level (i-1)th cache as is done here ?

asked Sep 29 in CO & Architecture by Harsh Kumar Junior (803 points) | 14 views

0 votes

0 answers

10

Load Back Cache
In the memory access time formula for the hierarchical cache - which is given as :$Emat = H1\times T1 + (1-H1)(H2\times (T1+T2) + (1-H2)\times (T1+T2+T3))$ (where Hi = Hit Ratio for the i-th level cache and Ti = Access time for i-th ... into the cache. Is my intuition correct? If yes, then what should be the Emat formula for Load Back cache ? Should we add extra Ti values?

asked Sep 29 in CO & Architecture by Harsh Kumar Junior (803 points) | 24 views

0 votes

1 answer

11

Cache - No. of Index Decoders
Certainly, the DM cache will require only single Cache Index decoder, whereas the Fully - Associative Cache will not require any. My question is - How many Index decoders do we need for K-way set associative cache? Is it just one or K ?

asked Sep 28 in CO & Architecture by Harsh Kumar Junior (803 points) | 31 views

0 votes

1 answer

12

Cache
What happens on write miss in a write back cache? First write in main memory then bring the block to cache (dirty bit = 0) or First bring the block to cache then write it (dirty bit = 1).

asked Sep 14 in CO & Architecture by MayankSharma (181 points) | 33 views

0 votes

0 answers

13

Computer Organisation- Cache

asked Sep 13 in CO & Architecture by sidlewis (359 points) | 22 views

0 votes

0 answers

14

Set Associative cache. Calculate cache capacity.

asked Sep 12 in CO & Architecture by Mk Utkarsh Boss (23.6k points) | 62 views

+2 votes

2 answers

15

#Cache
Consider a deirct map cache of 8 words, with block 2 words per Block. The following sequence of access to memory block 0,5,2,7,4,0 and 4 is repeated 10 times. Q1) number of compulsory miss? Q2) number of conflict misses? Q3) The number of capacity misses?

asked Sep 12 in CO & Architecture by Ayan21 (101 points) | 70 views

0 votes

0 answers

16

CACHE SELF DOUBT 2

asked Sep 10 in CO & Architecture by Balaji Jegan Active (3.1k points) | 43 views

0 votes

0 answers

17

CACHE SELF DOUBT 1

asked Sep 10 in CO & Architecture by Balaji Jegan Active (3.1k points) | 36 views

0 votes

1 answer

18

Self doubt
What is the difference between Memory access time and Memory latency. Memory access time : It is the time elapsed between CPU generating request for particular address and the time it locates it on Memory before actual transfer of bytes into registers. Is Memory Latency is same as Memory access time ???

asked Sep 9 in CO & Architecture by jatin khachane 1 Active (1.7k points) | 16 views

0 votes

1 answer

19

Cache

asked Sep 6 in CO & Architecture by Shivangi Parashar 2 (251 points) | 51 views

0 votes

0 answers

20

Cache-tag-directory
What is the size of tag in cache directory for direct and set-associative memory? For set-associative memory do we multiply by no of sets or no of blocks? According to me Size of Tag in cache directory = Number of tag bits(+ any extra bits like valid, ... = Number of tag bits(+ any extra bits like valid, modified etc) * number of sets Tag is associated with each block or set?

asked Sep 2 in CO & Architecture by Apoorva Jain (169 points) | 53 views

0 votes

1 answer

21

Miss latency and miss penalty
Are miss latency & miss penalty same in cache?if no then what's the difference???

asked Aug 29 in CO & Architecture by MayankSharma (181 points) | 58 views

+1 vote

1 answer

22

MadeEasy Test Series Tag,Set and Word field

asked Aug 23 in CO & Architecture by Mk Utkarsh Boss (23.6k points) | 77 views

0 votes

2 answers

23

MadeEasy Test Series Cache
Consider a memory access to main memory on a cache miss takes 100 ns and memory access to cache at cache hit takes 10 ns. If 75% processors memory request results in cache hit the average memory access time is _____ ns.

asked Aug 23 in CO & Architecture by Mk Utkarsh Boss (23.6k points) | 85 views

+1 vote

1 answer

24

Two level of cache
Consider a two level cache system. For 100 memory references 20 misses in 1st level cache,10 misses in second level cache. Miss penalty from second level to memory is 40 cycles. if Total average = 7.6 cycles, then hit time of second level cache ? Assume hit time of second level cache is two times the first level cache? Ans. 4

asked Aug 16 in CO & Architecture by Na462 Loyal (6.9k points) | 184 views

0 votes

1 answer

25

Explain this. And explain mapping. Just confuse between words per block. Per word n etc

asked Aug 15 in CO & Architecture by Aman mourya (21 points) | 29 views

0 votes

1 answer

26

Cache Capacity
if in a question it ask for cache capacity the is it calculated by follwing... cache capacity=cache size+ tag memory size+dirty bit cache capacity=tag bits * no. of cache lines which one is correct?

asked Aug 6 in CO & Architecture by Nihar Ranjan Panda (33 points) | 37 views

0 votes

1 answer

27

Multilevel Cache Access time
Ans. A

asked Aug 6 in CO & Architecture by Na462 Loyal (6.9k points) | 89 views

0 votes

1 answer

28

performance of cache memory
in cache performace i have confusion about where to use which formula like for write through whether use H (tc) + (1-H) (tc+m) or H (tc) + (1-H) (m) and how to identify whether cache memory is hierarchical or not from question can anyone give me all formula related to cache performance with explanation

asked Aug 6 in CO & Architecture by Rahul_Rathod_ (383 points) | 40 views

0 votes

0 answers

29

Direct Map Cache
Ans. 1

asked Aug 4 in CO & Architecture by Na462 Loyal (6.9k points) | 36 views

0 votes

0 answers

30

Cache GATE Doubt
In the following question if we consider for various data types such as char,float and int how would the answer vary? https://gateoverflow.in/1442/gate2013-20

asked Aug 3 in CO & Architecture by Devshree Dubey Boss (13.6k points) | 45 views

tags	tag:apple
author	user:martin
title	title:apple
content	content:apple
exclude	-tag:apple
force match	+apple
views	views:100
score	score:10
answers	answers:2
is accepted	isaccepted:true
is closed	isclosed:true

Recent questions tagged cache-memory

Slides

Recent Posts

Recent Blog Comments