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Recent questions tagged cache-memory
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GATE CSE 2021 Set 2 | Question: 19
Consider a set-associative cache of size $\text{2KB (1KB} =2^{10}$ bytes$\text{)}$ with cache block size of $64$ bytes. Assume that the cache is byte-addressable and a $32$ -bit address is used for accessing the cache. If the width of the tag field is $22$ bits, the associativity of the cache is _________
Consider a set-associative cache of size $\text{2KB (1KB} =2^{10}$ bytes$\text{)}$ with cache block size of $64$ bytes. Assume that the cache is byte-addressable and a $32$ -bit address is used for accessing the cache. If the width of the tag field is $22$ bits, the associativity of the cache is _________
asked
Feb 18
in
CO and Architecture
Arjun
608
views
gate2021-cse-set2
numerical-answers
co-and-architecture
cache-memory
1
vote
0
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2
GATE CSE 2021 Set 2 | Question: 27
Assume a two-level inclusive cache hierarchy, $L1$ and $L2$, where $L2$ is the larger of the two. Consider the following statements. $S_1$: Read misses in a write through $L1$ cache do not result in writebacks of dirty lines to the $L2$ $S_2$: Write ... false $S_1$ is false and $S_2$ is true $S_1$ is true and $S_2$ is true $S_1$ is false and $S_2$ is false
Assume a two-level inclusive cache hierarchy, $L1$ and $L2$, where $L2$ is the larger of the two. Consider the following statements. $S_1$: Read misses in a write through $L1$ cache do not result in writebacks of dirty lines to the $L2$ $S_2$: Write allocate policy must be ... $S_2$ is false $S_1$ is false and $S_2$ is true $S_1$ is true and $S_2$ is true $S_1$ is false and $S_2$ is false
asked
Feb 18
in
CO and Architecture
Arjun
467
views
gate2021-cse-set2
co-and-architecture
cache-memory
multilevel-cache
0
votes
3
answers
3
GATE CSE 2021 Set 1 | Question: 22
Consider a computer system with a byte-addressable primary memory of size $2^{32}$ bytes. Assume the computer system has a direct-mapped cache of size $\text{32 KB}$ ($\text{1 KB}$ = $2^{10}$ bytes), and each cache block is of size $64$ bytes. The size of the tag field is __________ bits.
Consider a computer system with a byte-addressable primary memory of size $2^{32}$ bytes. Assume the computer system has a direct-mapped cache of size $\text{32 KB}$ ($\text{1 KB}$ = $2^{10}$ bytes), and each cache block is of size $64$ bytes. The size of the tag field is __________ bits.
asked
Feb 18
in
CO and Architecture
Arjun
299
views
gate2021-cse-set1
co-and-architecture
cache-memory
numerical-answers
1
vote
1
answer
4
UGCNET-Oct2020-II: 5
Consider a machine with a byte addressable main memory of $2^{16}$ bytes block size of $8$ bytes. Assume that a direct mapped cache consisting of $32$ lines used with this machine. How many bits will be there in Tag, line and word field of format of main memory addresses? $8,5,3$ $8,6,2$ $7,5,4$ $7,6,3$
Consider a machine with a byte addressable main memory of $2^{16}$ bytes block size of $8$ bytes. Assume that a direct mapped cache consisting of $32$ lines used with this machine. How many bits will be there in Tag, line and word field of format of main memory addresses? $8,5,3$ $8,6,2$ $7,5,4$ $7,6,3$
asked
Nov 20, 2020
in
CO and Architecture
jothee
386
views
ugcnet-oct2020-ii
co-and-architecture
cache-memory
0
votes
1
answer
5
NIELIT 2017 OCT Scientific Assistant A (IT) - Section B: 22
In time division switches if each memory access takes $100\;ns $ and one frame period is $125\;\mu s,$ then the maximum number of lines that can be supported is $625$ lines $1250$ lines $2300$ lines $318$ lines
In time division switches if each memory access takes $100\;ns $ and one frame period is $125\;\mu s,$ then the maximum number of lines that can be supported is $625$ lines $1250$ lines $2300$ lines $318$ lines
asked
Apr 1, 2020
in
CO and Architecture
Lakshman Patel RJIT
424
views
nielit2017oct-assistanta-it
co-and-architecture
cache-memory
1
vote
2
answers
6
NIELIT 2017 DEC Scientific Assistant A - Section B: 56
In a particular system it is observed that, the cache performance gets improved as a result of increasing the block size of the cache. The primary reason behind this is : Programs exhibits temporal locality Programs have small working set Read operation is frequently required rather than write operation Programs exhibits spatial locality
In a particular system it is observed that, the cache performance gets improved as a result of increasing the block size of the cache. The primary reason behind this is : Programs exhibits temporal locality Programs have small working set Read operation is frequently required rather than write operation Programs exhibits spatial locality
asked
Mar 31, 2020
in
Operating System
Lakshman Patel RJIT
445
views
nielit2017dec-assistanta
operating-system
cache-memory
0
votes
3
answers
7
NIELIT 2016 DEC Scientist B (CS) - Section B: 37
The principle of locality of reference justifies the use of Non reusable Cache memory Virtual memory None of the above
The principle of locality of reference justifies the use of Non reusable Cache memory Virtual memory None of the above
asked
Mar 31, 2020
in
Operating System
Lakshman Patel RJIT
352
views
nielit2016dec-scientistb-cs
operating-system
cache-memory
0
votes
4
answers
8
NIELIT 2017 DEC Scientist B - Section B: 4
In a cache memory if total number of sets are ‘$s$’, then the set offset is: $2^8$ $\log_2s$ $s^2$ $s$
In a cache memory if total number of sets are ‘$s$’, then the set offset is: $2^8$ $\log_2s$ $s^2$ $s$
asked
Mar 30, 2020
in
CO and Architecture
Lakshman Patel RJIT
752
views
nielit2017dec-scientistb
co-and-architecture
cache-memory
0
votes
4
answers
9
NIELIT 2017 DEC Scientist B - Section B: 16
Which of the following is added to the page table in order to track whether a page of cache has been modified since it was read from the memory? Reference bit Dirty bit Tag bit Valid bit
Which of the following is added to the page table in order to track whether a page of cache has been modified since it was read from the memory? Reference bit Dirty bit Tag bit Valid bit
asked
Mar 30, 2020
in
Operating System
Lakshman Patel RJIT
974
views
nielit2017dec-scientistb
operating-system
memory-management
page-table
cache-memory
9
votes
4
answers
10
GATE CSE 2020 | Question: 30
A computer system with a word length of $32$ bits has a $16$ MB byte- addressable main memory and a $64$ KB, $4$-way set associative cache memory with a block size of $256$ ... set. $A3$ and $A4$ are mapped to the same cache set. $A1$ and $A3$ are mapped to the same cache set.
A computer system with a word length of $32$ bits has a $16$ MB byte- addressable main memory and a $64$ KB, $4$-way set associative cache memory with a block size of $256$ bytes. Consider the following four physical addresses represented in hexadecimal notation. $A1= 0x42C8A4$ ... same cache set. $A3$ and $A4$ are mapped to the same cache set. $A1$ and $A3$ are mapped to the same cache set.
asked
Feb 12, 2020
in
CO and Architecture
Arjun
6.5k
views
gate2020-cse
cache-memory
4
votes
2
answers
11
ISRO2020-47
How many total bits are required for a direct-mapped cache with $128$ KB of data and $1$ word block size, assuming a $32$-bit address and $1$ word size of $4$ bytes? $2$ Mbits $1.7$ Mbits $2.5$ Mbits $1.5$ Mbits
How many total bits are required for a direct-mapped cache with $128$ KB of data and $1$ word block size, assuming a $32$-bit address and $1$ word size of $4$ bytes? $2$ Mbits $1.7$ Mbits $2.5$ Mbits $1.5$ Mbits
asked
Jan 13, 2020
in
CO and Architecture
Satbir
1.6k
views
isro-2020
co-and-architecture
cache-memory
direct-mapping
normal
2
votes
3
answers
12
ISRO2020-43
Which of the following is an efficient method of cache updating? Snoopy writes Write through Write within Buffered write
Which of the following is an efficient method of cache updating? Snoopy writes Write through Write within Buffered write
asked
Jan 13, 2020
in
CO and Architecture
Satbir
1.3k
views
isro-2020
co-and-architecture
cache-memory
normal
0
votes
0
answers
13
Andrew S. Tanenbaum (OS) Edition 4 Exercise 4 Question 32 (Page No. 335)
The performance of a file system depends upon the cache hit rate (fraction of blocks found in the cache). If it takes $1\: msec$ to satisfy a request from the cache, but $40\: msec$ to satisfy a request if a disk read is needed ... request if the hit rate is $h.$ Plot this function for values of $h$ varying from $0$ to $1.0.$
The performance of a file system depends upon the cache hit rate (fraction of blocks found in the cache). If it takes $1\: msec$ to satisfy a request from the cache, but $40\: msec$ to satisfy a request if a disk read is needed, give a formula for the mean time required to satisfy a request if the hit rate is $h.$ Plot this function for values of $h$ varying from $0$ to $1.0.$
asked
Oct 27, 2019
in
Operating System
Lakshman Patel RJIT
131
views
tanenbaum
operating-system
file-system
cache-memory
descriptive
0
votes
0
answers
14
Andrew S. Tanenbaum (OS) Edition 4 Exercise 2 Question 10 (Page No. 174)
In the text it was stated that the model of Fig. $2-11(a)$ was not suited to a file server using a cache in memory. Why not? Could each process have its own cache?
In the text it was stated that the model of Fig. $2-11(a)$ was not suited to a file server using a cache in memory. Why not? Could each process have its own cache?
asked
Oct 24, 2019
in
Operating System
Lakshman Patel RJIT
73
views
tanenbaum
operating-system
process-and-threads
cache-memory
descriptive
0
votes
2
answers
15
Andrew S. Tanenbaum (OS) Edition 4 Exercise 1 Question 4 (Page No. 81)
To use cache memory, main memory is divided into cache lines, typically $32$ or $64$ bytes long. An entire cache line is cached at once. What is the advantage of caching an entire line instead of a single byte or word at a time?
To use cache memory, main memory is divided into cache lines, typically $32$ or $64$ bytes long. An entire cache line is cached at once. What is the advantage of caching an entire line instead of a single byte or word at a time?
asked
Oct 21, 2019
in
Operating System
Lakshman Patel RJIT
180
views
tanenbaum
operating-system
introduction
cache-memory
descriptive
1
vote
0
answers
16
Caching
Given the following information: TLB hit rate 95%, TLB access time is 1 cycle. cache hit rate 90 %, cache access time is 1 cycle. When TLB and cache both get miss; page fault rate is 1% The TLB access and acache access are ... cycles Access to hard drive requires 50,000 cycles. Compute the average memory access latencies when the cache is physically addresses (in cycles).
Given the following information: TLB hit rate 95%, TLB access time is 1 cycle. cache hit rate 90 %, cache access time is 1 cycle. When TLB and cache both get miss; page fault rate is 1% The TLB access and acache access are sequential. ... 75 cycles Access to hard drive requires 50,000 cycles. Compute the average memory access latencies when the cache is physically addresses (in cycles).
asked
Mar 10, 2019
in
CO and Architecture
s_dr_13
441
views
cache-memory
co-and-architecture
virtual-memory
tlb
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