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Recent questions tagged cache-memory

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GATE CSE 2023 | Question: 54
An $8$-way set associative cache of size $64 \mathrm{~KB} \;(1 \mathrm{~KB}=1024\; \text{bytes})$ is used in a system with $32$-bit address. The address is sub-divided into $\text{TAG, INDEX},$ and $\text{BLOCK OFFSET.}$ The number of bits in the $\text{TAG}$ is ___________.

admin asked in CO and Architecture Feb 15

by admin

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1 answer

2

#COA #CacheMemory
What is the default access method of Cache Memory? Simultaneous or Hierarchical?

iamsubhrajit asked in CO and Architecture Dec 31, 2022

by iamsubhrajit

134 views

2 votes

0 answers

3

cache miss question
In $T_{Read Avg}$, shouldn’t it be $T_{Read Avg}$ = (10*0.9) + 0.1*(10+100), because it must be checking the cache in case of cache miss too, right?

h4kr asked in CO and Architecture Dec 27, 2022

by h4kr

112 views

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1 answer

4

cache memory
Consider a RISC processor with an ideal CPI, where 25% of the total instructions are LOAD and STORE instruction. Time to accessing main memory is 100 clock cycles and accessing of the cache memory required 2 clock cycles. If cache miss rate is 2%, then the effective CPI for the system with the cache is ____.

someshawasthi asked in CO and Architecture Nov 17, 2022

by someshawasthi

131 views

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0 answers

5

cache memory
Consider a process where each instruction takes on average 3 cycle and there are 1.8 references to memory per instruction. A program with 50000 instruction is executed on this machine using a split cache of 32KB, obtained a 85% bit rate, 3ns bit time and 21ns miss penalty the execution time for the cache is ___ (μsec)

someshawasthi asked in CO and Architecture Nov 16, 2022

by someshawasthi

118 views

1 vote

1 answer

6

Zeal test series
A computer system uses $16-$bit memory addresses.It has a $16KB$ cache organized in a $4-$ way set associative manner with $64 $ bytes per cache block.Assume that size of each memory word is 2B .When a program is executed ,The processor read ... .All the above addresses shown in decimal values.Assume cache is initially empty .The number of addresses hit in the cache ?

Kabir5454 asked in CO and Architecture Nov 1, 2022

212 views

1 vote

1 answer

7

cache memory
THE size of memory required at cache controller to store the metadata is 2kbyte The metadata include tag bits 1 modified bit and 1 valid bit The cache contain 1KBlocks of 32 bytes each organized as directed mapped The size of Main memory is __ Mbytes?

Vaishnavi Gadhe asked in CO and Architecture Oct 25, 2022

by Vaishnavi Gadhe

192 views

2 votes

0 answers

8

Operating System: Self Doubt - Memory Management
Considering a system with Single-Level page table, with a TLB to reduce the access time of pages. A cache is also provided with the main memory. All the pages ultimately reside in MM. (assuming there's no page fault). Let, TLB Hit Ratio = x TLB Access ... for TLB miss it will be (a+c+p). But if this is true, why can't we store Page Table in a Cache?

DebRC asked in Operating System Sep 14, 2022

by DebRC

165 views

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Recent questions tagged cache-memory