Register

Slides

Recent questions tagged cache-memory

11 votes
1 answer
121
GATE Overflow Test Series | Mock GATE | Test 2 | Question: 62
Consider a $2$-way set-associative cache of size $32$ KB and block size $64$ ... times. If the number of conflict misses and compulsory misses are $A$ and $B$ respectively, $A + 2B =$ _________
Consider a $2$-way set-associative cache of size $32$ KB and block size $64$ bytes and using LRU replacement. Initially the cache is empty. The following sequence of acce...
User Avatar
6 votes
1 answer
129
GATE Overflow Test Series | Computer Organization and Architecture | Test 1 | Question: 25
Consider a direct mapped cache of size $16$ KB and block size $64$ ... the number of conflict misses and compulsory misses are $A$ and $B$ respectively, $2A + B =$ _____
Consider a direct mapped cache of size $16$ KB and block size $64$ bytes and using LRU replacement. Initially the cache is empty. The following sequence of access to memo...
User Avatar
10 votes
1 answer
133
GATE Overflow Test Series | Computer Organization and Architecture | Test 1 | Question: 30
Consider a CPU with an average CPI of $1.4$ ... allocate policy with the probability of a cache block being dirty being $0.15$ (round off to $2$ decimal places).
Consider a CPU with an average CPI of $1.4$ when all memory accesses hit on the cache.Assume an instruction mix$$\begin{array}{|c | c|}\hline\text{ALU }& 45\%\\\text{LOAD...
User Avatar
1 votes
2 answers
134
NIELIT 2017 OCT Scientific Assistant A (IT) - Section B: 22
In time division switches if each memory access takes $100\;ns $ and one frame period is $125\;\mu s,$ then the maximum number of lines that can be supported is $625$ lines $1250$ lines $2300$ lines $318$ lines
In time division switches if each memory access takes $100\;ns $ and one frame period is $125\;\mu s,$ then the maximum number of lines that can be supported is$625$ line...
User Avatar
0 votes
3 answers
136
NIELIT 2016 DEC Scientist B (CS) - Section B: 37
The principle of locality of reference justifies the use of Non reusable Cache memory Virtual memory None of the above
The principle of locality of reference justifies the use ofNon reusableCache memoryVirtual memoryNone of the above
User Avatar
0 votes
4 answers
137
NIELIT 2017 DEC Scientist B - Section B: 4
In a cache memory if total number of sets are ‘$s$’, then the set offset is: $2^8$ $\log_2s$ $s^2$ $s$
In a cache memory if total number of sets are ‘$s$’, then the set offset is:$2^8$$\log_2s$$s^2$$s$
User Avatar
1 votes
2 answers
138
NIELIT 2017 DEC Scientist B - Section B: 16
Which of the following is added to the page table in order to track whether a page of cache has been modified since it was read from the memory? Reference bit Dirty bit Tag bit Valid bit
Which of the following is added to the page table in order to track whether a page of cache has been modified since it was read from the memory?Reference bitDirty bitTag ...
User Avatar
7 votes
5 answers
141
ISRO2020-47
How many total bits are required for a direct-mapped cache with $128$ KB of data and $1$ word block size, assuming a $32$-bit address and $1$ word size of $4$ bytes? $2$ Mbits $1.7$ Mbits $2.5$ Mbits $1.5$ Mbits
How many total bits are required for a direct-mapped cache with $128$ KB of data and $1$ word block size, assuming a $32$-bit address and $1$ word size of $4$ bytes?$2$ M...
User Avatar
2 votes
3 answers
142
ISRO2020-43
Which of the following is an efficient method of cache updating? Snoopy writes Write through Write within Buffered write
Which of the following is an efficient method of cache updating?Snoopy writesWrite throughWrite withinBuffered write
User Avatar
1 votes
0 answers
144
Andrew S. Tanenbaum (OS) Edition 4 Exercise 2 Question 10 (Page No. 174)
In the text it was stated that the model of Fig. $2-11(a)$ was not suited to a file server using a cache in memory. Why not? Could each process have its own cache?
In the text it was stated that the model of Fig. $2-11(a)$ was not suited to a file server using a cache in memory. Why not? Could each process have its own cache?
User Avatar
1 votes
1 answer
146
WEST BENGAL SET COMPUTER SCIENCE
A CPU has 32 bit-memory address and eacch word has size of 1 byte.
A CPU has 32 bit-memory address and eacch word has size of 1 byte.
User Avatar
0 votes
1 answer
148
Self-doubt
How to improve cache hit rate in case of transfer of element from 2-D array to matrix.? (Consider the column major order in 2D array)
How to improve cache hit rate in case of transfer of element from 2-D array to matrix.? (Consider the column major order in 2D array)
User Avatar
0 votes
0 answers
149
Cache Memory and Arrays
Can someone please provide a link to an article or a video explaining cache and arrays concept. Im having a hard time understanding that concept.
Can someone please provide a link to an article or a video explaining cache and arrays concept. Im having a hard time understanding that concept.
User Avatar
1 votes
1 answer
150
Self-doubt
What is meant by cache index? Please state by example.
What is meant by cache index? Please state by example.
User Avatar
Page: