Recent questions tagged cache-memory / GATE Overflow for GATE CSE

1 votes

0 answers

151

Caching
Given the following information: TLB hit rate 95%, TLB access time is 1 cycle. cache hit rate 90 %, cache access time is 1 cycle. When TLB and cache both get miss; page fault rate is 1% The TLB access and acache access are ... cycles Access to hard drive requires 50,000 cycles. Compute the average memory access latencies when the cache is physically addresses (in cycles).

Given the following information: • TLB hit rate 95%, TLB access time is 1 cycle. • cache hit rate 90 %, cache access time is 1 cycle. • When TLB and cache both get ...

s_dr_13

1.1k views

s_dr_13 asked Mar 10, 2019

1 votes

1 answer

152

Self-doubt
What does tag number signifies in line in cache?

What does tag number signifies in line in cache?

Anuranjan

332 views

Anuranjan asked Mar 9, 2019

0 votes

0 answers

153

Self doubt(Hamacher and Zaky)
Memory is word addressable with 16 bit addresses Word size=16 bits Each block is of size 16 bits. The cache contains 8 blocks. What is the address division for: 1>direct. 2>associative 3>2-way set associative cache

Memory is word addressable with 16 bit addressesWord size=16 bitsEach block is of size 16 bits.The cache contains 8 blocks.What is the address division for:1>direct.2>as...

DIYA BASU

588 views

DIYA BASU asked Feb 17, 2019

1 votes

1 answer

154

#ComputerArchitecture
If a computer executes a store, should it place the data into the cache or main memory? Cache only Main memory only Both cache and main memory Cache only OR Both cache and main memory

If a computer executes a store, should it place the data into the cache or main memory?Cache onlyMain memory onlyBoth cache and main memoryCache only OR Both cache and ma...

Reshu $ingh

310 views

Reshu $ingh asked Feb 14, 2019

23 votes

8 answers

155

GATE CSE 2019 | Question: 1
A certain processor uses a fully associative cache of size $16$ kB, The cache block size is $16$ bytes. Assume that the main memory is byte addressable and uses a $32$-bit address. How many bits are required for the Tag and the Index fields respectively in the addresses ... $0$ bits $28$ bits and $4$ bits $24$ bits and $4$ bits $28$ bits and $0$ bits

A certain processor uses a fully associative cache of size $16$ kB, The cache block size is $16$ bytes. Assume that the main memory is byte addressable and uses a $32$-bi...

Arjun

18.0k views

Arjun asked Feb 7, 2019

56 votes

11 answers

156

GATE CSE 2019 | Question: 45
A certain processor deploys a single-level cache. The cache block size is $8$ words and the word size is $4$ bytes. The memory system uses a $60$-MHz clock. To service a cache miss, the memory controller first takes $1$ cycle to accept ... for the memory system when the program running on the processor issues a series of read operations is ______$\times 10^6$ bytes/sec.

A certain processor deploys a single-level cache. The cache block size is $8$ words and the word size is $4$ bytes. The memory system uses a $60$-MHz clock. To service a ...

Arjun

20.5k views

Arjun asked Feb 7, 2019

1 votes

2 answers

157

gate 2019
Consider the cache memory size of 16kb, and cache block size is 16 bytes. The processor generates the physical address of 32 bits. Assume the cache is fully associative. What are the TAG and index bits __________ (A) 28 and 4bits (B) 28 and 0bits (C) 24 and 4bits (D) 24 and 0bits

Consider the cache memory size of 16kb, and cache block size is 16 bytes. The processor generates the physical address of 32 bits. Assume the cache is fully associative. ...

sahil_malik

1.1k views

sahil_malik asked Feb 4, 2019

1 votes

1 answer

158

self doubt
Main memory=512 words. block size=8 words. cache size =32 words There is an array A[100] and each element is 4 words then what is the hit ratio for the following loop. for(i=0;i<=9;i++) { for(j=0;j<=9;j=j+2) { A[i][j]=A[i][j]+20; } }

Main memory=512 words.block size=8 words.cache size =32 wordsThere is an array A[100] and each element is 4 words then what is the hit ratio for the following loop.for...

DIYA BASU

328 views

DIYA BASU asked Feb 3, 2019

0 votes

1 answer

159

self doubt
Main memory=512 words. block size=8 words. cache size =32 words what is tag,line no.,block offset bits

Main memory=512 words.block size=8 words.cache size =32 wordswhat is tag,line no.,block offset bits

DIYA BASU

382 views

DIYA BASU asked Feb 3, 2019

0 votes

0 answers

160

self doubt
https://gateoverflow.in/2308/gate1993-11 This question can also be solved as a probability question where the random space contains (M1),(M1,M2),(M1,M2,M3) and let X be the random variable which gives the time for any of the three options selected from the ... space and correspondingly we give the PMF for each time selected and then we find the expectation?? Am I correct with my logic??

https://gateoverflow.in/2308/gate1993-11 This question can also be solved as a probability question where the random space contains (M1),(M1,M2),(M1,M2,M3) and let X be t...

DIYA BASU

203 views

DIYA BASU asked Feb 2, 2019

0 votes

1 answer

161

SELF DOUBT
If main memory size=128KB. cache size 16KB . block size 256B. And memory is word addressable each word is 4B . Then is the address divided into : tag=3bits. line no=6 bits block offset=6 bits???(PLEASE VERIFY) We use DIRECT MAPPING.

If main memory size=128KB.cache size 16KB .block size 256B.And memory is word addressable each word is 4B .Then is the address divided into :tag=3bits.line no=6 bitsblock...

DIYA BASU

323 views

DIYA BASU asked Feb 2, 2019

3 votes

1 answer

162

ME adv mock
A hypothetical processor on cache read miss requires one clock to send an address to Main Memory (MM) and eight clock cycles to access a 64-bit word from MM to processor cache. Miss rate of read is decreased from 14.8% to 2.6% when line size ... words. The speed up of processor is achieved in dealing with average read miss after increasing the line size is_____ (Upto 2 decimal places)

A hypothetical processor on cache read miss requires one clock to send an address to Main Memory (MM) and eight clock cycles to access a 64-bit word from MM to processor ...

newdreamz a1-z0

875 views

newdreamz a1-z0 asked Feb 1, 2019

0 votes

1 answer

163

GRADEUP
For a 4 bit set associative cache 10 bits are required as index to specify cache block. The main memory is of size 4G x 32. Size of cache memory is? Answer is 4096*49. Please explain the notation also.

For a 4 bit set associative cache 10 bits are required as index to specify cache block. The main memory is of size 4G x 32. Size of cache memory is? Answer is 4096*49. Pl...

Aman Janko

508 views

Aman Janko asked Feb 1, 2019

1 votes

2 answers

164

made easy test series
please provide a detailed solution

please provide a detailed solution

Vignaneswarkrishna

617 views

Vignaneswarkrishna asked Feb 1, 2019

1 votes

0 answers

165

Cache
Please tell what happens to hit rate, hit time, compulsory miss rate, conflict miss rate, capacity miss rate, miss time on : 1. Increasing Cache size 2. Increasing Block size 3. Increasing number of lines 4. Increasing Associativity

Please tell what happens to hit rate, hit time, compulsory miss rate, conflict miss rate, capacity miss rate, miss time on :1. Increasing Cache size2. Increasing Block si...

Balaji Jegan

577 views

Balaji Jegan asked Jan 31, 2019

0 votes

0 answers

166

Cache acess
I know the acess time to a sequential acess cache is given as Hitrate*(Cache acess time)+ Miss rate*(Cachec acess time + Mem acess time) Now in question if they explicitly say in case of miss data is obtained from memory and put into cache and again ... , will my formula change Hirate(Cache acess time)+ Misseate* ( Cache acess time+ Mem acess time + Cache acess time) pls help me

I know the acess time to a sequential acess cache is given asHitrate*(Cache acess time)+ Miss rate*(Cachec acess time + Mem acess time)Now in question if they explicitly ...

Aravind Adithya 1

360 views

Aravind Adithya 1 asked Jan 31, 2019

4 votes

1 answer

167

MadeEasy Test Series 2019: CO & Architecture- Cache Memory
Consider a n-way cache with 'x blocks of 64 words each. The main memory of the system is having 8 million words. Size of the tag field is 16 bits and additional memory required for tags is 1024 bytes. What will be the values of n and x respectively? Answer 256 512

Consider a n-way cache with 'x blocks of 64 words each. The main memory of the system is having 8 million words. Size of the tag field is 16 bits and additional memory re...

Ram Swaroop

1.6k views

Ram Swaroop asked Jan 30, 2019

5 votes

1 answer

168

MadeEasy Test Series 2019: CO & Architecture - Cache Memory
A CPU cache is organized into 2 level cache L1 and L2 The penalty for L1 cache miss and L2 cache miss are 60 and 30 respectively for 1200 memory references The hit time of L1 and L2 are 5 and 10 clock cycles and penalty for L2 cache miss to main memory is 70 clock cycles. The average memory access time will be

A CPU cache is organized into 2 level cache L1 and L2 The penalty for L1 cache miss and L2 cache miss are 60 and 30 respectively for 1200 memory references The hit time o...

Ram Swaroop

1.3k views

Ram Swaroop asked Jan 29, 2019

0 votes

1 answer

169

MadeEasy Full Length Test 2019: CO & Architecture - Cache Memory
Consider a 2 way set associative cache with 4 blocks. The memory block requests in the order. 4,6,3,8,5,6,0,15,6,17,20,15,0,8 If LRU is used for block replacement then memory set 17 will be in the cache block ____. (PS: the given answer is 1)

Consider a 2 way set associative cache with 4 blocks. The memory block requests in the order.4,6,3,8,5,6,0,15,6,17,20,15,0,8If LRU is used for block replacement then memo...

snaily16

810 views

snaily16 asked Jan 28, 2019

0 votes

0 answers

170

Computer organisation cache
Why can't we have n-levels of cache ?

Why can't we have n-levels of cache ?

Priyansh Singh

619 views

Priyansh Singh asked Jan 27, 2019

0 votes

1 answer

171

ME Test series question
A computer uses two level cache L1 and L2 and in 2000 memory references there are 320 misses in L1 cache and 150 misses in L2lcache. If the miss penalty of L2 is 300 clock cycles, hit time of L1 is 1 clock cycle and hit time of L2 is 10 clock cycles what is the average memory access time?

A computer uses two level cache L1 and L2 and in 2000 memory references there are 320 misses in L1 cache and 150 misses in L2lcache. If the miss penalty of L2 is 300 cloc...

Shankar Kakde

375 views

Shankar Kakde asked Jan 25, 2019

0 votes

1 answer

172

Cache Organization
Can any one help me out with this question : This was asked in MadeEasy CBT held on 23rd jan

Can any one help me out with this question :This was asked in MadeEasy CBT held on 23rd jan

Nandkishor3939

1.1k views

Nandkishor3939 asked Jan 25, 2019

0 votes

1 answer

173

MadeEasy Full Length Test 2019: CO & Architecture - Cache Memory
All is fine but how did they calculate the miss rate of level 2 cache (L2) i.e.how is m2=0.46875?

All is fine but how did they calculate the miss rate of level 2 cache (L2) i.e.how is m2=0.46875?

Iamniks4

683 views

Iamniks4 asked Jan 24, 2019

1 votes

1 answer

174

Ace Test Series: CO & Architecture - Cache Memory

Na462

745 views

Na462 asked Jan 21, 2019

1 votes

0 answers

175

Ace Test Series: CO & Architecture - Cache Misses Type

Na462

929 views

Na462 asked Jan 21, 2019

0 votes

0 answers

176

ME TEST
A byte addressable computer has a small data cache capable of holding 16 32-bit words. Each cache block consist of four 32 bits words. For the following sequence of main memory addresses (in hexadecimal). The conflict miss if 2-way set associative LRU cache is used is_____ 100,108, 114 ... what will be the address partition look like. 1. tag(7) set(1) offset(4) 2. tag(7) set(1) offset(2)

A byte addressable computer has a small data cache capable of holding 16 32-bit words. Each cache block consist of four 32 bits words. For the following sequence of main ...

newdreamz a1-z0

378 views

newdreamz a1-z0 asked Jan 21, 2019

0 votes

0 answers

177

find conflict misses
here it is given byte addressable. So these locations refer to words or byte location. What are set, block fields here : number of words or number of bytes for these location.

here it is given byte addressable. So these locations refer to words or byte location. What are set, block fields here : number of words or number of bytes for these loca...

bts1jimin

456 views

bts1jimin asked Jan 17, 2019

0 votes

0 answers

178

ME-MT-CO+OS
consider a 2-level $L_1$ and $L_2$ memory hierarchy system.The associativity of $L_1$ towards processor is more .$L_1$(cache ) has accessing time of 15 ns and $L_2$ (main memory) has an accessing time of 100 ns .writing takes 30 ns for $L_1$ and 150 ns for $L_2$.assume ... simultaneously so $T_w=150 ns$ $T_r=.7*15ns+.3*(100ns+15ns)=45ns$ $T_{avg}=.5*45+.5*150=97.5ns$ please verify it.

consider a 2-level $L_1$ and $L_2$ memory hierarchy system.The associativity of $L_1$ towards processor is more .$L_1$(cache ) has accessing time of 15 ns and $L_2$ (main...

Prateek Raghuvanshi

329 views

Prateek Raghuvanshi asked Jan 17, 2019

1 votes

1 answer

179

Applied Course | Mock GATE | Test 1 | Question: 54
The common pattern in code for using cache systems looks like the following. In this example get_from_cache() returns zero when the data was not in the cache. int lookup(int key) { int data; data = get_from_cache(key); if (data == 0) { data = get_from_backing_store( ... $1 \: ms$ $6 \: ms$ $30 \: ms$ $95 \: ms$

The common pattern in code for using cache systems looks like the following. In this example get_from_cache() returns zero when the data was not in the cache.int lookup(i...

Applied Course

450 views

Applied Course asked Jan 16, 2019

0 votes

1 answer

180

Computer system organization cache memory
Assume that A, B , and C are memory addresses each of which are in different block of memory. Further assume A, B , C are generated in a uniformly random way. What is the probability that the second instance of "B" will be a hit on a 4-line direct-mapped cache?

Assume that A, B , and C are memory addresses each of which are in different block of memory. Further assume A, B , C are generated in a uniformly random way.What is th...

Nikita Shadija

387 views

Nikita Shadija asked Jan 16, 2019

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