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Recent questions tagged cache-memory

4 votes
1 answer
394
Associative mapping in cache
If main memory $=128 \ KB$ and cache memory is of $2KB$ with $16B$ lines .and uses associative mapping . What would be the # of bits used for Tag for each block?
If main memory $=128 \ KB$ and cache memory is of $2KB$ with $16B$ lines .and uses associative mapping .What would be the # of bits used for Tag for each block?
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4 votes
1 answer
396
Cache size
If a 16 – way set associative cache is made up of 64 bit words, 16 words per line and 8192 sets, how big is the cache in mega bytes?
If a 16 – way set associative cache is made up of 64 bit words, 16 words per line and 8192 sets, how big is the cache in mega bytes?
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3 votes
1 answer
397
MadeEasy Test Series: CO & Architecture - Cache Memory
The statement " Direct mapped cache, may produce more misses if programs refers to memory words that occupy a same tag value." is true or false ?
The statement " Direct mapped cache, may produce more misses if programs refers to memory words that occupy a same tag value." is true or false ?
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1 votes
1 answer
401
Comp.Architecture-2
Here $128$ block actually refers to Lines right? So it should be $8+4+7=19$ Assume memory is word addessable?Thanks!
Here $128$ block actually refers to Lines right?So it should be $8+4+7=19$ Assume memory is word addessable?Thanks!
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0 votes
0 answers
403
Cache
Consider a architecture where we have one level of cache and X is the clock rate,now on a same architecture if clock rate becomes 2X. what are the affect on these things: a)miss penalty b)cycles per cache c)CPI and what will be the speed up ?
Consider a architecture where we have one level of cache and X is the clock rate,now on a same architecture if clock rate becomes 2X.what are the affect on these things:a...
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7 votes
1 answer
404
ISRO-DEC2017-37
A two-way set associative cache memory unit with a capacity of $16\, KB$ is built using a block size of $8\, words.$ The word length is $32-bits.$ The physical address space is $4\, GB.$ The number of bits in the TAG, SET fields are $20,7$ $19,8$ $20,8$ $21,9$
A two-way set associative cache memory unit with a capacity of $16\, KB$ is built using a block size of$8\, words.$ The word length is $32-bits.$ The physical address spa...
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2 votes
3 answers
407
Write Trough
Do we consider hierarchical model or simultaneous access model for write through ?
Do we consider hierarchical model or simultaneous access model for write through ?
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0 votes
1 answer
408
SSC-IMD-2017-01
If the main memory is of 8K bytes and the cache memory is of 2K words. It uses associative mapping. Then each word of cache memory shall be 1) 11 bits 2) 21 bits 3) 16 bits 4) 20 bits
If the main memory is of 8K bytes and the cache memory is of 2K words. It uses associative mapping. Then each word of cache memory shall be1) 11 bits2) 21 bits3) 16 bits4...
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1 votes
1 answer
409
types of miss in cache
a direct-mapped cache of the size of 4 blocks. The main memory block access sequences are 0,1,2,3,4,1,2,3,0,4,0 No. of compulsory misses, conflict misses and capacity misses?
a direct-mapped cache of the size of 4 blocks. The main memory block access sequences are 0,1,2,3,4,1,2,3,0,4,0 No. of compulsory misses, conflict misses and capacity mis...
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0 votes
0 answers
410
Cache
State True of false STATEMENT : Conflict and Inference misses can be reduced by doubling the associativity of a cache design. what is Inference misses here ? I Know it is true for conflict misses.
State True of falseSTATEMENT : Conflict and Inference misses can be reduced by doubling the associativity of a cache design.what is Inference misses here ? I Know it is t...
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0 votes
0 answers
411
cache
what is cache hit time and what is cache hit latency ? are they both same ?
what is cache hit time and what is cache hit latency ? are they both same ?
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0 votes
1 answer
412
CO Question
How many total bits are required for a direct-mapped cache with 16 KB of data and 4-word blocks, assuming a 32-bit address?
How many total bits are required for a direct-mapped cache with 16 KB of dataand 4-word blocks, assuming a 32-bit address?
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0 votes
0 answers
418
Cache Organization
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