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Recent questions tagged cache-memory

4 votes
3 answers
421
cache hit ratio
Consider an array A[200] and each element occupies 8-words. A 64-word cache is used and divided into 16-word blocks. What is the hit ratio for the following code segment: for(int i=0; i<200; i++) A[i] = A[i]+5 0.85 0.65 0.95 0.75
Consider an array A[200] and each element occupies 8-words. A 64-word cache is used and divided into 16-word blocks. What is the hit ratio for the following code segment:...
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1 votes
0 answers
422
Hit latency in Cache
How to approach hit latency problems in cache mapping techniques. Please explain with an example. Thank in advance.
How to approach hit latency problems in cache mapping techniques.Please explain with an example.Thank in advance.
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0 votes
1 answer
423
MadeEasy Subject Test: CO & Architecture - Cache Memory
ASAIK for Tavg(read) = T(read) = HR(read) * Tc + (1-HR) * (Tc+Tm) but while calculating they have neglected Tc in (Tc+Tm)... Please verify ??
ASAIK for Tavg(read) = T(read) = HR(read) * Tc + (1-HR) * (Tc+Tm)but while calculating they have neglected Tc in (Tc+Tm)...Please verify ??
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4 votes
2 answers
424
COA:- Memory size
A computer has 170 different instructions.Word size is 4B and one word instruction has 2 address fields.One adress for register and one address for memory.If there are 37 registers,then memory size in KB is?
A computer has 170 different instructions.Word size is 4B and one word instruction has 2 address fields.One adress for register and one address for memory.If there are 37...
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0 votes
1 answer
425
COA:- Average stalls per instruction
What will be L1 miss rate? I think it is 80/3600 ,but then answer did not match. But if i take 80/2000,then it matches with the given answer
What will be L1 miss rate? I think it is 80/3600 ,but then answer did not match. But if i take 80/2000,then it matches with the given answer
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2 votes
1 answer
435
COA: Average Memory Access Time
My Solution: E.M.A.T = HitTimeL1 + MissRateL1x( HitTimeL2 + MissRateL2xMissPenaltyL2) = 1 + $\frac{16}{100}$(5 + $\frac{8}{16}$*50) = 1 + .16(30) = 5.8 Please, someone validate this solution!
My Solution:E.M.A.T = HitTimeL1 + MissRateL1x( HitTimeL2 + MissRateL2xMissPenaltyL2) = 1 + $\frac{16}{100}$(5 + $\frac{8}{16}$*50) = 1 + .16(30)...
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1 votes
0 answers
436
cache
I read in cache Effective time = hit ratio * cache access time + miss ratio*memory access time why not in miss penalty the additional searching in cache considered i.e. Penalty = memory access time + cache access time as unnecessary we need to search cache right?
I read in cache Effective time = hit ratio * cache access time + miss ratio*memory access timewhy not in miss penalty the additional searching in cache consider...
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2 votes
0 answers
437
Doubt in direct cache mapping
The direct mapped cache uses M main memory blocks and N cache blocks, for a given Physical Address it resulted T tag bits and placed in P cache block. Which main memory words May respond to this Physical Address? Block size is P words.
The direct mapped cache uses M main memory blocks and N cache blocks, for a given Physical Address it resulted T tag bits and placed in P cache block. Which main memory w...
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1 votes
0 answers
438
Multilevel cache
In multilevel cache do we use hierarchical access memory or simultaneous access memory concept? Please mention formula for calculating Avg access time of the system using multi level cache design.
In multilevel cache do we use hierarchical access memory or simultaneous access memory concept?Please mention formula for calculating Avg access time of the system using ...
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1 votes
1 answer
443
co&architecture # cache-memory
what part in the address of following mapping techniques 1. direct mapped 2.set associative 3. Associative used by cache controller for indexing into the cache directory?
what part in the address of following mapping techniques1. direct mapped2.set associative3. Associativeused by cache controller for indexing into the cache directory?
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2 votes
0 answers
444
Cache Memory
There are 4 types of caches Virtually Indexed Virtually Tagged Virtually indexed Physically Tagged Physically Indexed Virtually Tagged Physically Indexed Physically Tagged Plz give some clear thought, to distinguish these 4 type of cache
There are 4 types of cachesVirtually Indexed Virtually TaggedVirtually indexed Physically TaggedPhysically Indexed Virtually TaggedPhysically Indexed Physically TaggedPlz...
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3 votes
1 answer
450
cache memory
In k-way set associative mapping , the tag field contains 8 bits and 64 no. of sets and propagation delay of a comparator is k/20 nsec and propagation delay of 2*1 multiplexer is k/10 nsec. then what will be the total delay? (let k=8)
In k-way set associative mapping , the tag field contains 8 bits and 64 no. of sets and propagation delay of a comparator is k/20 nsec and propagation delay of 2*1 multip...
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