Recent questions tagged cache-memory / GATE Overflow for GATE CSE

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1 answer

481

[COA] Hamacher Example 5.2,Page 322,Fifth edition
Writing the example in short words; Cache Access =1ns Main Memory Access =10 clock cycles Time to load word into the cache = 17 cycles 30% Instructions perform Memory read and write. Instruction cache Hit rate=.95 and Data cache ... same for both read and write access. Find the performance gain if we use system with cache over system without cache.

Writing the example in short words;Cache Access =1nsMain Memory Access =10 clock cyclesTime to load word into the cache = 17 cycles30% Instructions perform Memory read an...

rahul sharma 5

639 views

rahul sharma 5 asked May 29, 2017

1 votes

1 answer

482

Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 29
Suppose in a system we store data using arrays, we have $2$ arrays A1 and A2. Array A1 contains $256$ elements of size $4$ bytes each. The first element is stored at physical address $4096$ ... of bytes that will be written to memory during execution of the loop is : $256$ $1$ $0$ $2048$

Suppose in a system we store data using arrays, we have $2$ arrays A1 and A2. Array A1 contains $256$ elements of size $4$ bytes each. The first element is stored at phy...

Bikram

529 views

Bikram asked May 27, 2017

0 votes

2 answers

483

Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 27
Consider a memory hierarchy system consisting of two levels. The access time of level $1$ is $2$ ns. The miss penalty (The time to get data from level $2$, in case of miss) is $100$ ns. If the average memory ... the average access time to $40 \%$, the probability that valid data found in level $1$ is ___________ $\%$

Consider a memory hierarchy system consisting of two levels. The access time of level $1$ is $2$ ns. The miss penalty (The time to get data from level $2$, in case of mis...

Bikram

388 views

Bikram asked May 27, 2017

2 votes

2 answers

484

Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 25
Suppose there are $500$ memory references in which $50$ misses in the $1$st level cache and $20$ misses in the $2$nd level cache . Let the miss penalty from L2 cache to memory is $100$ cycles. ... cycles. If there are $2.5$ memory reference/instruction , average number of stall cycles per instruction will be __________

Suppose there are $500$ memory references in which $50$ misses in the $1$st level cache and $20$ misses in the $2$nd level cache . Let the miss penalty from L2 cache to m...

Bikram

579 views

Bikram asked May 27, 2017

0 votes

2 answers

485

Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 23
Consider a two level memory hierarchy having only one level cache and main memory. Cache and Main memory access times are $20$ ns and $120$ ns/word respectively. The size of cache block is $4$ words . If main memory is referenced $40 \%$ of the times, then average access time is _______ ns

Consider a two level memory hierarchy having only one level cache and main memory. Cache and Main memory access times are $20$ ns and $120$ ns/word respectively. The size...

Bikram

527 views

Bikram asked May 27, 2017

1 votes

1 answer

486

Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 22
Suppose that a direct-mapped cache has $2^{10}$ cache lines, with $2^4$ bytes of data per cache line. If the cache is used to store blocks for a byte addressable memory of size $2^{30}$ bytes, then number of bytes of space will be required for storing the tags is ________ (put the integer value)

Suppose that a direct-mapped cache has $2^{10}$ cache lines, with $2^4$ bytes of data per cache line. If the cache is used to store blocks for a byte addressable memory ...

Bikram

308 views

Bikram asked May 27, 2017

0 votes

1 answer

487

Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 16
Consider the following statements about the Locality of Reference principle used in the computer memory systems. The principal states that an already accessed memory location is accessed further again and it is also more likely that ... the above statements is/are TRUE? I only II only II and III only I and III only

Consider the following statements about the Locality of Reference principle used in the computer memory systems.The principal states that an already accessed memory locat...

Bikram

271 views

Bikram asked May 27, 2017

0 votes

4 answers

488

Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 15
Consider a $2$ - way set associative cache memory with $4$ sets and total $8$ cache blocks $(0 - 7)$. Main memory has $64$ blocks $(0 - 63)$. If LRU policy is used for replacement and cache is initially empty then total number of conflict cache ... block references is: $0 \ 5 \ 9 \ 13 \ 7 \ 0 \ 15 \ 25$ $2$ $3$ $0$ $1$

Consider a $2$ – way set associative cache memory with $4$ sets and total $8$ cache blocks $(0 – 7)$. Main memory has $64$ blocks $(0 - 63)$. If LRU policy is used fo...

Bikram

916 views

Bikram asked May 27, 2017

0 votes

1 answer

489

Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 12
A $4$ way set associative cache with a size of $32$ KB has line size $16$ Bytes. There is a Byte addressable main memory with a size of $256$ MB, then which of the following Main Memory block is mapped on to the set $'0'$ of Cache Memory? $(FCEE90B)16$ $(FECF10C)16$ $(CFEE09B)16$ $(CDDE00B)16$

A $4$ way set associative cache with a size of $32$ KB has line size $16$ Bytes. There is a Byte addressable main memory with a size of $256$ MB, then which of the follow...

Bikram

320 views

Bikram asked May 27, 2017

0 votes

1 answer

490

Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 8
A two-dimensional array int $a [32] [32]$ where each element takes $2$ byte, cache size $2^{12}$ bytes and line size is $2^6$ bytes. The following program segment is stored in the direct mapped cache. ... ][ j] = 0 If initially cache is empty then total number of compulsory cache miss for storing above array is ________

A two-dimensional array int $a [32] [32]$ where each element takes $2$ byte, cache size $2^{12}$ bytes and line size is $2^6$ bytes. The following program segment is st...

Bikram

381 views

Bikram asked May 27, 2017

1 votes

2 answers

491

Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 7
A system is having $4$ way set associative cache of $256$ KB. The cache line size is $8$ words and each word has $32$ bits. Suppose memory addresses are $64$ bits long. Then number of bits required for the index field of the cache memory is _______

A system is having $4$ way set associative cache of $256$ KB. The cache line size is $8$ words and each word has $32$ bits. Suppose memory addresses are $64$ bits long. T...

Bikram

647 views

Bikram asked May 27, 2017

0 votes

1 answer

492

Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 4
Consider a computer system that has a cache with $512$ blocks, each of which can store $32$ bytes of data. All addresses are byte addresses.Then to which cache line will the memory address OXFBFC map to if the cache is direct mapped and ... respectively? $\text{DBA, 3C}$ $\text{1DA, 1D}$ $\text{1DF, 1F}$ $\text{1CF, 3E}$

Consider a computer system that has a cache with $512$ blocks, each of which can store $32$ bytes of data. All addresses are byte addresses.Then to which cache line will ...

Bikram

273 views

Bikram asked May 27, 2017

1 votes

1 answer

493

Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 2
$16$kB cache with line size $64$B uses $4$ – way set associative mapping. Main memory is $8$ MB and byte addressable. The size of extra space needed for storing tag information in bytes is _________

$16$kB cache with line size $64$B uses $4$ – way set associative mapping. Main memory is $8$ MB and byte addressable. The size of extra space needed for storing tag inf...

Bikram

360 views

Bikram asked May 27, 2017

0 votes

1 answer

494

[COA] Cache terminology definitions
Please give definition for:- 1. Principle of inclusion 2. Cache coherence

Please give definition for:-1. Principle of inclusion2. Cache coherence

rahul sharma 5

367 views

rahul sharma 5 asked May 26, 2017

0 votes

0 answers

495

[COA] Cache Set associative mapping
Question 1:- Consider a 32-bit microprocessor that has an on-chip 16-KByte four-way set-associative cache. Assume that the cache has a line size of four 32-bit words. Draw a block diagram of this cache showing its organization and how the different ... of bits taken were 6 ? How can i identify whether we need to convert to byte addressable from word size or not?

Question 1:- Consider a 32-bit microprocessor that has an on-chip 16-KByte four-way set-associativecache. Assume that the cache has a line size of four 32-bit words. Draw...

rahul sharma 5

1.1k views

rahul sharma 5 asked May 24, 2017

1 votes

1 answer

496

Hamacher COA 5.7,p-362
A computer uses a small direct-mapped cache between the main memory and the processor. The cache has four 16-bit words, and each word has an associated 13-bit tag, as shown in Figure P5.2a. When a miss occurs during a read operation, the ... the cache is $1\tau$. Calculate the execution time for each pass. Ignore the time taken by the processor between memory cycles.

A computer uses a small direct-mapped cache between the main memory and the processor. The cache has four 16-bit words, and each word has an associated 13-bit tag, as sho...

rahul sharma 5

978 views

rahul sharma 5 asked May 23, 2017

0 votes

3 answers

497

[COA][ Hamacher 1.6] Cache memory
1.6 Suppose that execution time for a program is directly proportional to instruction access time and that access to an instruction in the cache is 20 times faster than access to an instruction in the main memory. Assume that a requested instruction ... added only one then please explain why? part B) Does doubling cache means access time of cache is also doubled?

1.6 Suppose that execution time for a program is directly proportional to instruction access time and that access to an instruction in the cache is 20 times faster than a...

rahul sharma 5

1.9k views

rahul sharma 5 asked May 22, 2017

1 votes

1 answer

498

[COA] Cache write through in hierarchical design
For hierarchical access and write-through,The average write time is given by: 1. Twt=H×Tmemory+(1−H)×(Tcache+Tmemory) 2. Twt=Tmemory Which one to refer in question?Can we ignore Tcache and use the second one? Please clarify?

For hierarchical access and write-through,The average write time is given by: 1. Twt=H×Tmemory+(1−H)×(Tcache+Tmemory)2. Twt=TmemoryWhich one to refer in question?Can ...

rahul sharma 5

932 views

rahul sharma 5 asked May 20, 2017

0 votes

0 answers

499

[COA] Memory Access
A computer has a cache, main memory, and a disk used for virtual memory. If a referenced word is in the cache,Cpu access it from cache.. If it is in main memory but not in the cache, 50 ns are needed to load it into the cache, and then the ... word on this system.Cache access time is 5 ns ,Main memory access time is 10 ns. Edit:- Disk accessed was mentioned twice.Updated it

A computer has a cache, main memory, and a disk used for virtual memory. If a referenced word is in the cache,Cpu access it from cache.. If it is in main memory but not i...

rahul sharma 5

1.1k views

rahul sharma 5 asked May 20, 2017

3 votes

1 answer

500

[CO] Memory Organization
3 level memory has the following specifications:- Level AccessTime/Word Block Size in words Hit Ratio 1 20 ns - .7 2 100 ns 2 .9 3 200 ns 4 1 If the referenced block is not in L1,then transfer from L2 to L1,If not in L2,then transfer from L3 to L2 to L1.How long will it take to access a block?

3 level memory has the following specifications:-LevelAccessTime/WordBlock Size in wordsHit Ratio120 ns-.72100 ns2.93200 ns41If the referenced block is not in L1,then tra...

rahul sharma 5

2.1k views

rahul sharma 5 asked May 19, 2017

10 votes

3 answers

501

ISRO2017-21
A cache memory needs an access time of $30$ ns and main memory $150$ ns, what is average access time of CPU (assume hit ratio $= 80\%)?$ $60$ ns $30$ ns $150$ ns $70$ ns

A cache memory needs an access time of $30$ ns and main memory $150$ ns, what is average access time of CPU (assume hit ratio $= 80\%)?$$60$ ns$30$ ns$150$ ns$70$ ns

sh!va

13.3k views

sh!va asked May 7, 2017

4 votes

2 answers

502

Patterson Hennessey
Which of the following cache designer guidelines are generally valid? 1. The shorter the memory latency, the smaller the cache block 2. The shorter the memory latency, the larger the cache block 3. The higher the memory bandwidth, the smaller the cache block 4. The higher the memory bandwidth, the larger the cache block

Which of the following cache designer guidelines are generally valid?1. The shorter the memory latency, the smaller the cache block2. The shorter the memory latency, th...

kauray

1.5k views

kauray asked May 1, 2017

0 votes

1 answer

503

Testbook Test Series: CO & Architecture - Cache Memory
If a 16-way Set Associative cache is made up of 64 bit words , 16 words per line and 8192 sets, How big is the cache in Megabytes ?

If a 16-way Set Associative cache is made up of 64 bit words , 16 words per line and 8192 sets,How big is the cache in Megabytes ?

Devwritt

1.8k views

Devwritt asked Apr 29, 2017

0 votes

0 answers

504

Block replacement in cache
How we replace blocks in k-way set associative cache ? What strategy we follow?

How we replace blocks in k-way set associative cache ? What strategy we follow?

elakashi sharma

307 views

elakashi sharma asked Apr 27, 2017

2 votes

1 answer

505

gate2000-12 cache memory
An instruction pipeline has five stages where each stage take 2 nanoseconds and all instruction use all five stages. Branch instructions are not overlapped. i.e., the instruction after the branch is not fetched till the branch instruction is ... 50% of the conditional branch instructions are such that the branch is taken, calculate the average instruction execution time.

An instruction pipeline has five stages where each stage take 2 nanoseconds and all instruction use all five stages. Branch instructions are not overlapped. i.e., the ins...

shal

466 views

shal asked Apr 1, 2017

2 votes

1 answer

506

False sharing in cache Line
Here is pseudo code for a multiprocessing purpose: set_num_threads(NUM_THREADS); double sum=0.0; sum_local[NUM_THREADS]; parallel region { int this_thread_id = get_thread_number(); // returns 0 to (no_of_threads-1) sum_local[this_thread_id] = 0.0; for (i ... I think frequent DRAM write back causing the problem, but not very clear, though. please explain a bit. @Arjun Sir

Here is pseudo code for a multiprocessing purpose:set_num_threads(NUM_THREADS); double sum=0.0; sum_local[NUM_THREADS]; parallel region { int this_thread_id = get_thread_...

dd

1.1k views

dd asked Mar 5, 2017

3 votes

1 answer

507

Write back Cache with write allocate policy
Consider a computer with the following features: 90% of all memory accesses are found in the cache (hit ratio = 0.9); The block size is 2 words and the whole block is read on any miss; The CPU sends references to the cache at ... uses write allocate on a write miss. Calculate the percentage of the bus bandwidth used on the average if cache is WRITE BACK:

Consider a computer with the following features:90% of all memory accesses are found in the cache (hit ratio = 0.9);The block size is 2 words and the whole block is read ...

sh!va

1.7k views

sh!va asked Mar 2, 2017

62 votes

10 answers

508

GATE CSE 2017 Set 1 | Question: 54
A cache memory unit with capacity of $N$ words and block size of $B$ words is to be designed. If it is designed as a direct mapped cache, the length of the $\textsf{TAG}$ field is $10$ bits. If the cache unit is now designed as a $16$-way set-associative cache, the length of the $\textsf{TAG}$ field is ____________ bits.

A cache memory unit with capacity of $N$ words and block size of $B$ words is to be designed. If it is designed as a direct mapped cache, the length of the $\textsf{TAG}$...

Arjun

19.7k views

Arjun asked Feb 14, 2017

91 votes

9 answers

509

GATE CSE 2017 Set 1 | Question: 51
Consider a $2$-way set associative cache with $256$ blocks and uses $\text{LRU}$ replacement. Initially the cache is empty. Conflict misses are those misses which occur due to the contention of multiple blocks for the same cache set. Compulsory ... $10$ times. The number of conflict misses experienced by the cache is _________ .

Consider a $2$-way set associative cache with $256$ blocks and uses $\text{LRU}$ replacement. Initially the cache is empty. Conflict misses are those misses which occur d...

Arjun

38.6k views

Arjun asked Feb 14, 2017

29 votes

8 answers

510

GATE CSE 2017 Set 2 | Question: 53
Consider a machine with a byte addressable main memory of $2^{32}$ bytes divided into blocks of size $32$ bytes. Assume that a direct mapped cache having $512$ cache lines is used with this machine. The size of the tag field in bits is _______

Consider a machine with a byte addressable main memory of $2^{32}$ bytes divided into blocks of size $32$ bytes. Assume that a direct mapped cache having $512$ cache line...

Madhav

9.5k views

Madhav asked Feb 14, 2017

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