Login
Register
Dark Mode
Brightness
Profile
Edit Profile
Messages
My favorites
My Updates
Logout
Slides
A Simple Illustration
Cache Memory
Recent questions tagged cache-memory
78
votes
5
answers
511
GATE CSE 2017 Set 2 | Question: 45
The read access times and the hit ratios for different caches in a memory hierarchy are as given below: ... and $40\%$ are for memory operand fetch. The average read access time in nanoseconds (up to $2$ decimal places) is _________
The read access times and the hit ratios for different caches in a memory hierarchy are as given below:$$\begin{array}{|l|c|c|} \hline \text {Cache} & \text{Read access ...
Madhav
29.7k
views
Madhav
asked
Feb 14, 2017
CO and Architecture
gatecse-2017-set2
co-and-architecture
cache-memory
numerical-answers
+
–
67
votes
6
answers
512
GATE CSE 2017 Set 2 | Question: 29
In a two-level cache system, the access times of $L_1$ and $L_2$ caches are $1$ and $8$ clock cycles, respectively. The miss penalty from the $L_2$ cache to main memory is $18$ clock cycles. The miss rate of $L_1$ cache is twice that of $L_2$. The average ... respectively are $0.111$ and $0.056$ $0.056$ and $0.111$ $0.0892$ and $0.1784$ $0.1784$ and $0.0892$
In a two-level cache system, the access times of $L_1$ and $L_2$ caches are $1$ and $8$ clock cycles, respectively. The miss penalty from the $L_2$ cache to main memory i...
Arjun
28.3k
views
Arjun
asked
Feb 14, 2017
CO and Architecture
gatecse-2017-set2
cache-memory
co-and-architecture
normal
+
–
102
votes
9
answers
513
GATE CSE 2017 Set 1 | Question: 25
Consider a two-level cache hierarchy with $L1$ and $L2$ caches. An application incurs $1.4$ memory accesses per instruction on average. For this application, the miss rate of $L1$ cache is $0.1$; the $L2$ cache experiences, on average, $7$ misses per $1000$ instructions. The miss rate of $L2$ expressed correct to two decimal places is ________.
Consider a two-level cache hierarchy with $L1$ and $L2$ caches. An application incurs $1.4$ memory accesses per instruction on average. For this application, the miss rat...
Arjun
24.1k
views
Arjun
asked
Feb 14, 2017
CO and Architecture
gatecse-2017-set1
co-and-architecture
cache-memory
numerical-answers
+
–
0
votes
2
answers
514
GATE 2017 Set 2 - COA
In Gate 2017 Afternoon session there was a que where they asked for Tag Size in bit. So in this que tag bit was 18 . But to calculate tag size i think we should multiply it with number of Lines i.e 18*29 Note : No. of Lines was given in que. Is my approach is right?
In Gate 2017 Afternoon session there was a que where they asked for Tag Size in bit.So in this que tag bit was 18 .But to calculate tag size i think we should multiply it...
Anup patel
1.4k
views
Anup patel
asked
Feb 12, 2017
CO and Architecture
cache-memory
+
–
2
votes
1
answer
515
Test by Bikram | Mock GATE | Test 3 | Question: 10
A byte-addressed computer system has a cache with $512$ blocks, each of which can store $32$ $bytes$ of data. To which cache line will the memory address $’0\text{x}FBFC’$ map onto if the cache is direct-mapped and is $8$ way set–associative, respectively? $DBA, 3C$ $1DA, 1D$ $1DF, 1F$ $1CF, 3E$
A byte-addressed computer system has a cache with $512$ blocks, each of which can store $32$ $bytes$ of data.To which cache line will the memory address $’0\text{x}FBFC...
Bikram
269
views
Bikram
asked
Feb 9, 2017
CO and Architecture
tbb-mockgate-3
co-and-architecture
cache-memory
+
–
2
votes
2
answers
516
Test Series
Consider a 4-way set associative cache that has 8-lines, with perfect LRU cache replacement and supports a block size of 16-bytes. For the following memory access pattern (shown as byte addresses), find the hit ratio? 3, 5, 6, 21, 32, 14, 5, 10, 11, 12
Consider a 4-way set associative cache that has 8-lines, with perfect LRU cache replacement and supports a block size of 16-bytes. For the following memory access pattern...
Rounak Agarwal
722
views
Rounak Agarwal
asked
Feb 8, 2017
CO and Architecture
co-and-architecture
cache-memory
+
–
0
votes
1
answer
517
Memory addressing
The cache can hold 512 KB. Data is transferred between main memory and cache in blocks of 16 byte each. The main memory consist 4 Gbyte. If the cache memory is 2 way set associative then the hexadecimal main memory address (ABCABCCBA)H is mapped to which cache set? I think answer should be 3CCB
The cache can hold 512 KB. Data is transferred between main memory and cache in blocks of 16 byte each. The main memory consist 4 Gbyte. If the cache memory is 2 way set ...
Pankaj Joshi
1.3k
views
Pankaj Joshi
asked
Feb 3, 2017
CO and Architecture
co-and-architecture
cache-memory
+
–
5
votes
1
answer
518
True or false
$S_1$: When the write-through protocol used in the simultaneous access memory organization then the hit ratio for write request is 100%. $S_2$: Conflict and Inference misses can be reduced by double the associativity of a cache design. $S_3$: In ... are required in the direct, associative and set associative cache designs to replace the cache blocks. Which of the following is false?
$S_1$: When the write-through protocol used in the simultaneous access memory organization then the hit ratio for write request is 100%.$S_2$: Conflict and Inference miss...
Supremo
2.2k
views
Supremo
asked
Jan 30, 2017
CO and Architecture
cache-memory
write-through
write-back
direct-mapping
+
–
0
votes
1
answer
519
Cache Associative memory
A cache is having 64KB capacity 128 byte lines and is 4-way set associative the sytem containing the cache uses 32 bit address. How many sets does the cache have ?
A cache is having 64KB capacity 128 byte lines and is 4-way set associative the sytem containing the cache uses 32 bit address. How many sets does the cache have ?
vishal8492
5.2k
views
vishal8492
asked
Jan 29, 2017
CO and Architecture
co-and-architecture
cache-memory
+
–
2
votes
2
answers
520
GATEBOOK MOCK TEST 1
A processor with a word addressable memory has a two-way set associative cache. A cache line is one word and, so a cache entry contains a set of words. If there are M words of memory and C cache entries, How many words of memory map to the same cache entry? (A) C/2 (B) M/2C (C) M/C (D) 2M/C
A processor with a word addressable memory has a two-way set associative cache. A cache line is one word and, so a cache entry contains a set of words. If there are M wor...
Nitesh Methani
1.5k
views
Nitesh Methani
asked
Jan 29, 2017
CO and Architecture
gatebook
cache-memory
+
–
0
votes
1
answer
521
madeeasy
My question is how does cache block size affect the placement of blocks/addresses in cache? Example: here 2 word cache block vs 1 word cache block size. What will be the difference?
My question is how does cache block size affect the placement of blocks/addresses in cache? Example: here 2 word cache block vs 1 word cache block size. What will be the ...
sidsunny
285
views
sidsunny
asked
Jan 26, 2017
CO and Architecture
made-easy-test-series
co-and-architecture
cache-memory
+
–
2
votes
1
answer
522
CO Test 1 q31
Consider a CPU that executes at a clock rate of 200MHz(5ns per cycle) with a single level cache. CPI execution i.e. CPI with ideal memory is 1.1. Instruction mix are 50% arithmetic/Logical, 30% load/store, 20% control instruction. Assume the cache miss rate is 15% and a miss penalty of 50 cycles. The number of times cpu with ideal memory is faster when no miss occurs _______
Consider a CPU that executes at a clock rate of 200MHz(5ns per cycle) with a single level cache. CPI execution i.e. CPI with ideal memory is 1.1. Instruction mix are 50% ...
Vasu_gate2017
2.5k
views
Vasu_gate2017
asked
Jan 25, 2017
CO and Architecture
co-and-architecture
cache-memory
+
–
0
votes
0
answers
523
set associative cache
debanjan sarkar
306
views
debanjan sarkar
asked
Jan 24, 2017
CO and Architecture
least-recently-used
cache-memory
+
–
0
votes
1
answer
524
MadeEasy Subject Test: CO & Architecture - Cache Memory
debanjan sarkar
191
views
debanjan sarkar
asked
Jan 24, 2017
CO and Architecture
made-easy-test-series
co-and-architecture
cache-memory
+
–
0
votes
0
answers
525
MadeEasy Subject Test: CO & Architecture - Cache Memory
debanjan sarkar
189
views
debanjan sarkar
asked
Jan 24, 2017
CO and Architecture
made-easy-test-series
co-and-architecture
cache-memory
+
–
1
votes
1
answer
526
Test by Bikram | Mock GATE | Test 2 | Question: 40
Consider a set associative cache memory with $8$ cache blocks $(0 - 7)$ and main memory with $128$ blocks. The following block requests are made by the $CPU$ ($\text{LRU}$ ... pair in which main memory block $7$ is present is: $3, 7$ $3, 6$ $2, 5$ $7$ is recently replaced
Consider a set associative cache memory with $8$ cache blocks $(0 - 7)$ and main memory with $128$ blocks. The following block requests are made by the $CPU$ ($\text{LRU}...
Bikram
387
views
Bikram
asked
Jan 24, 2017
CO and Architecture
tbb-mockgate-2
co-and-architecture
page-replacement
cache-memory
+
–
2
votes
2
answers
527
Test by Bikram | Mock GATE | Test 2 | Question: 26
The designers of a computer must select a cache system. They have two options. In first design they uses a direct-mapped cache containing $2$ words per cache line. It would have an instruction miss rate of $3%$ and a data miss rate of $8%$. In second design they uses a $2$- ... $D1 = 0.70, D2 = 0.40$ $D1 = 1.10, D2 = 0.40$ $D1 = 0.70, D2 = 0.48$
The designers of a computer must select a cache system. They have two options.In first design they uses a direct-mapped cache containing $2$ words per cache line. It woul...
Bikram
623
views
Bikram
asked
Jan 24, 2017
GATE
tbb-mockgate-2
co-and-architecture
cache-memory
+
–
1
votes
2
answers
528
Test by Bikram | Mock GATE | Test 2 | Question: 15
A certain computer has a $TLB$ cache, a one-level physically-addressed data cache, $DRAM$, and a disk backing store for virtual memory. The processor loads the instruction below and then begins to execute it. LW R3, 0(R4) $[$ LW ... one data cache miss can occur. If a page fault occurs, then a data cache miss definitely does not occur as well.
A certain computer has a $TLB$ cache, a one-level physically-addressed data cache, $DRAM$, and a disk backing store for virtual memory. The processor loads the instructio...
Bikram
711
views
Bikram
asked
Jan 24, 2017
GATE
tbb-mockgate-2
co-and-architecture
cache-memory
translation-lookaside-buffer
+
–
4
votes
3
answers
529
Test by Bikram | Mock GATE | Test 2 | Question: 6
The designers of a cache system wants to reduce the number of cache misses that occur in a certain group of programs. Which of the following statements is/are correct regarding what designers can do? If compulsory misses are most common, then ... provide more flexibility when a collision occurs. I, II, and III I and II only II and III only III only
The designers of a cache system wants to reduce the number of cache misses that occur in a certain group of programs.Which of the following statements is/are correct rega...
Bikram
561
views
Bikram
asked
Jan 24, 2017
GATE
tbb-mockgate-2
co-and-architecture
cache-memory
+
–
3
votes
0
answers
530
Set Associative Cache [GateBook]
biranchi
381
views
biranchi
asked
Jan 24, 2017
CO and Architecture
co-and-architecture
cache-memory
+
–
2
votes
1
answer
531
MadeEasy Subject Test: CO & Architecture - Cache Memory
Suppose that in 250 memory references there are 30 misses in first level cache and 10 misses in second level cache. Assume that miss penalty from the L2 cache memory are 50 cycles. The hit time of L2 cache is 10 cycles ... 5 cycles. If there are 1.25 memory references per instruction, then the average stall cycles per instruction is ________.
Suppose that in 250 memory references there are 30 misses in first level cache and 10 misses in second level cache. Assume that miss penalty from the L2 cache memory are ...
Pankaj Joshi
874
views
Pankaj Joshi
asked
Jan 23, 2017
CO and Architecture
made-easy-test-series
co-and-architecture
multilevel-cache
cache-memory
+
–
0
votes
1
answer
532
cache miss
harshit agarwal
448
views
harshit agarwal
asked
Jan 23, 2017
CO and Architecture
co-and-architecture
cache-memory
+
–
3
votes
1
answer
533
MadeEasy CBT 2017: CO & Architecture - Cache Memory
Dulqar
874
views
Dulqar
asked
Jan 22, 2017
CO and Architecture
made-easy-test-series
cbt-2017
co-and-architecture
cache-memory
+
–
0
votes
0
answers
534
MadeEasy Subject Test: CO & Architecture - Cache Memory
# plz check???
# plz check???
Hradesh patel
222
views
Hradesh patel
asked
Jan 21, 2017
CO and Architecture
made-easy-test-series
co-and-architecture
cache-memory
+
–
16
votes
0
answers
535
Discussion regarding Cache Memory
What is the size of $MUX$ needed in direct mapped cache ? For ex :- | Tag = $17$ | line = $10$ | word = $5$ | Diagram Reference :- Direct mapped cache with multi word block In set associative cache, Do MUX and OR ... MUX and OR gate work parallely, then Hit latency includes both delays ? Diagram Reference :- - Also, any reason/explaination regarding below image ?
What is the size of $MUX$ needed in direct mapped cache ?For ex :- | Tag = $17$ | line = $10$ | word = $5$ |Diagram Reference :- Direct mapped cache with multi word bloc...
Kapil
2.3k
views
Kapil
asked
Jan 21, 2017
CO and Architecture
cache-memory
co-and-architecture
direct-mapping
+
–
0
votes
1
answer
536
Ace Test Series: CO & Architecture - Cache Memory
shubhamdarokar
406
views
shubhamdarokar
asked
Jan 18, 2017
CO and Architecture
ace-test-series
co-and-architecture
cache-memory
+
–
1
votes
1
answer
537
Operating System
Çșȇ ʛấẗẻ
373
views
Çșȇ ʛấẗẻ
asked
Jan 18, 2017
Operating System
cache-memory
paging
operating-system
+
–
1
votes
0
answers
538
CO Doubt
Cache Doubt
Cache Doubt
pps121
187
views
pps121
asked
Jan 17, 2017
CO and Architecture
cache-memory
+
–
1
votes
2
answers
539
Test by Bikram | Mock GATE | Test 1 | Question: 51
The access time of cache memory is $10$ $ns$ and main memory is $100$ $ns$. It is estimated that $80 \%$ of memory requests are for read and remaining are for write. The hit ratio for read access only is $0.9$. A write through procedure is used. Pages are always available in cache for write operation. Then, the average access time is ______ $ns$.
The access time of cache memory is $10$ $ns$ and main memory is $100$ $ns$. It is estimated that $80 \%$ of memory requests are for read and remaining are for write. The ...
Bikram
1.4k
views
Bikram
asked
Jan 16, 2017
GATE
tbb-mockgate-1
numerical-answers
cache-memory
co-and-architecture
+
–
1
votes
3
answers
540
Test by Bikram | Mock GATE | Test 1 | Question: 30
A computer has a cache, main memory, and a disk used for virtual memory. If a referenced word is in the cache, $10$ $ns$ are required to access it. If it is main memory but not in the cache, total $200$ $ns$ are needed to load it ... is found in the given level of the memory hierarchy. $732000$ $ns$ $485750$ $ns$ $500012$ $ns$ $23009$ $ns$
A computer has a cache, main memory, and a disk used for virtual memory. If a referenced word is in the cache, $10$ $ns$ are required to access it. If it is main memory b...
Bikram
737
views
Bikram
asked
Jan 16, 2017
GATE
tbb-mockgate-1
cache-memory
co-and-architecture
+
–
Page:
« prev
1
...
13
14
15
16
17
18
19
20
21
22
23
...
25
next »
Email or Username
Show
Hide
Password
I forgot my password
Remember
Log in
Register