Recent questions tagged cache-memory / GATE Overflow for GATE CSE

3 votes

0 answers

541

Cache memory
Cache is having 80% hit ratio only for read operations. Suppose cache access require 20 cycles and main memory require 120 cycles. If there is a cache miss and the data is first transferred to the cache from main memory then cpu access it from cache. If ... be the hit ratio when both read and write are considered? Assume write through technique is used. What is the average access time?

Cache is having 80% hit ratio only for read operations. Suppose cache access require 20 cycles and main memory require 120 cycles. If there is a cache miss and the data i...

Hardik Vagadia

1.5k views

Hardik Vagadia asked Jan 14, 2017

0 votes

1 answer

542

Virtual Gate Test Series: CO & Architecture - Cache Access
my question is even in case of a miss the cache will still be accessed and then main memory, right? please explain this when to consider higher memory level access time and when not to consider it

my question is even in case of a miss the cache will still be accessed and then main memory, right? please explain this when to consider higher memory level access time a...

Pankaj Joshi

307 views

Pankaj Joshi asked Jan 13, 2017

2 votes

1 answer

543

CO Moemory Hierarchy
Consider a 3 Level Memory System with the following specifications (H1,H2,H3) = (0.8,0.9,1) (T1,T2,T3) = (2,100,500) nano sec / word IF there is miss at L1 and Hit at L2 .A 2-Word block must be transfered from L2 to L1 IF there is miss at both ... Taken Given that the data width between L1 to L2 and L2 to L3 is 4 Word block is Tavg-2 What is the ratio of Tavg-1 to Tavg-2

Consider a 3 Level Memory System with the following specifications(H1,H2,H3) = (0.8,0.9,1)(T1,T2,T3) = (2,100,500) nano sec / wordIF there is miss at L1 and Hit at L2 .A...

Dulqar

1.3k views

Dulqar asked Jan 13, 2017

2 votes

1 answer

544

Memory Mapping
The width of the physical address on a machine is 40 bits. The width of the tag field in a 512 KB 8-way set associative cache is ?

The width of the physical address on a machine is 40 bits. The width of the tag field in a 512 KB 8-way set associative cache is ?

Sarvottam Patel

707 views

Sarvottam Patel asked Jan 11, 2017

2 votes

1 answer

545

set associative Cache
What is organisation of set associative cache.. How Mux, Decoders, comparators are used?

What is organisation of set associative cache..How Mux, Decoders, comparators are used?

vaishali jhalani

1.7k views

vaishali jhalani asked Jan 11, 2017

1 votes

2 answers

546

TestBook Test Series
Consider the following information about a hypothetical organization. Assume the cache is physically addressed TLB:hit rate is 95%,access time is 1 cycle Cache: hit rate is 90%,access time is 1 cycle When TLB and cache both get miss,page fault rate is 1% ... cycles Page table is always kept in main memory. Compute the average memory access time? 1 cycle 2 cycle 3 cycle 4 cycle

Consider the following information about a hypothetical organization.Assume the cache is physically addressedTLB:hit rate is 95%,access time is 1 cycleCache: hit rate is ...

vnc

667 views

vnc asked Jan 11, 2017

0 votes

3 answers

547

Cache memory
Is it compulsory that the block sizes of the main memory and the cache memory are always equal?

Is it compulsory that the block sizes of the main memory and the cache memory are always equal?

Hardik Vagadia

1.0k views

Hardik Vagadia asked Jan 9, 2017

0 votes

0 answers

548

Cache Miss
Can anyone Explain why Cache misses are reduced when Associativity is high

Can anyone Explain why Cache misses are reduced when Associativity is high

shivanisrivarshini

249 views

shivanisrivarshini asked Jan 9, 2017

5 votes

3 answers

549

CO Cache stall cycles
Suppose that in 500 memory references there are 50 misses in the first level cache and 20 misses in the second level cache.Assume miss penalty from the L2 cache to memory is 100 cycles.The hit time of L2 cache is 20 cycle.The hit time of the L1 cache is 10 cycles. If there are 2.5 memory references per instruction.How many average stall cycles per instructions are there?

Suppose that in 500 memory references there are 50 misses in the first level cache and 20 misses in the second level cache.Assume miss penalty from the L2 cache to memory...

Prajwal Bhat

3.9k views

Prajwal Bhat asked Jan 7, 2017

1 votes

2 answers

550

miss ratio

vaishali jhalani

703 views

vaishali jhalani asked Jan 7, 2017

6 votes

1 answer

551

cache memory access time with interleaved memory modules
Carl Hamachar : Time to access information in the cache = $1$ cycle Main memory is constructed as $4$ interleaved modules Cache block size of $8$ words. In a cache miss, the first word of a block can be accessed from main ... $B$. What is the average memory access time for instruction?

Carl Hamachar :Time to access information in the cache = $1$ cycleMain memory is constructed as $4$ interleaved modulesCache block size of $8$ words.In a cache miss, the ...

dd

2.2k views

dd asked Jan 6, 2017

1 votes

1 answer

552

cache and main memory
Assume the following performance characteristics on a cache read miss: one clock cycle to send an address to main memory and four clock cycles to access a 32-bit word from main memory and transfer it to the processor and cache. What is the miss ... per word transfer? What would be the answer if memory is not interleaved and word access is done sequentially from main memory?

Assume the following performance characteristics on a cache read miss:one clock cycle to send an address to main memory and four clock cycles to access a 32-bit word from...

dd

3.0k views

dd asked Jan 6, 2017

2 votes

0 answers

553

Test Series question
A 2-way set associative write back cache with true LRU replacement requires 15 * 29 bits to implement its tag store per set (including bits for valid, dirty and LRU). The cache is virtually indexed, physically tagged. The virtual address space is 1 MB, page ... cache block size is 8 bytes and is byte-addressable. What is the maximum size of the data store of the cache in bytes?

A 2-way set associative write back cache with true LRU replacement requires 15 * 29 bits to implement its tag store per set (including bits for valid, dirty and LRU). The...

bad_engineer

386 views

bad_engineer asked Jan 5, 2017

4 votes

1 answer

554

Simultaneous vs Hierarchical Memory Access using Write back and Write through policy
Please some one share good resource to read Simultaneous and heirarchial memory access with write back and write through cache.There are already some posts asking the same.I am not asking formulas:).Some good authentic resouce to read.Didnt find this much in William stallings.

Please some one share good resource to read Simultaneous and heirarchial memory access with write back and write through cache.There are already some posts asking the sam...

rahul sharma 5

1.5k views

rahul sharma 5 asked Jan 3, 2017

2 votes

1 answer

555

CO Cache Memory Access
In a certain system the main memory access time is 100 ns. The cache is 10 time faster than the main memory and uses the write though protocol. If the hit ratio for read request is 0.92 and 85% of the memory requests generated by the CPU are for read, ... write; then the average time consideration both read and write requests is a) 28.95ns b) 348.47ns c) 29.62ns d) 296.2ns

In a certain system the main memory access time is 100 ns. The cache is 10 time faster than the main memory and uses the write though protocol. If the hit ratio for read ...

rahul sharma 5

2.8k views

rahul sharma 5 asked Jan 3, 2017

0 votes

0 answers

556

CO Cache Memory
Please suggest a good source for understanding cache circuitory from GATE point of view (not mapping alone). And please validate the following. If someone can wrtite a blog post regarding this it will be very helpful for everyone. Direct Mapped Cache: No of Comparators ... set) And One K-1 Multiplexors. This is done to enable parallel checking of blocks in a set. Thanks in advance.

Please suggest a good source for understanding cache circuitory from GATE point of view (not mapping alone). And please validate the following. If someone can wrtite a bl...

Kaushik.P.E

198 views

Kaushik.P.E asked Jan 2, 2017

1 votes

0 answers

557

Cache Memory
Given the following benchmark code, and assume that all variables except array locations resides in registers, a double variable occupies 8 bytes and the array A, B and C are placed consecutively in memory, answer the following questions double A[1024], B[ ... Assume a virtually addressed two-way set associative cache of capacity 8 KB and 64 byte blocks, compute the overall miss rate.

Given the following benchmark code, and assume that all variables except array locations resides in registers, a double variable occupies 8 bytes and the array A, B and C...

Aghori

446 views

Aghori asked Dec 26, 2016

1 votes

1 answer

558

Computing Effective Memory access time - Cache organization
Consider the following information about a hypothetical processor. Assume the cache is physically addressed TLBHit Rate: 95% access time 1 cycle Cache Hit Rate: 90% access time 1 cycle when tlb and cache both get miss, page fault rate 1% TLB access and ... 1 + .1(5+ .01(100) ) = 2.675 Could someone pls point out the flaw in the logic?

Consider the following information about a hypothetical processor.Assume the cache is physically addressedTLBHit Rate: 95% access time 1 cycleCache Hit Rate: 90% access t...

yg92

1.3k views

yg92 asked Dec 26, 2016

1 votes

0 answers

559

MadeEasy Subject Test: CO & Architecture - Cache Memory
Consider a cache memory having hit ratios for read and write operations are80% and 90% respectively. If there is miss (either for read and for write ) entire 2word block is to be through from main memory to cache. Let there are 30% updations. The ... /sec. (b) 16.5 million words /sec. (c)14.5million words /sec. (d)13.5 million words /sec

Consider a cache memory having hit ratios for read and write operations are80% and 90% respectively. If there is miss (either for read and for write ) entire 2word block ...

Kamal Raj Praveen

200 views

Kamal Raj Praveen asked Dec 22, 2016

0 votes

0 answers

560

William Stalling cache memory || 4.22
A computer has a cache, main memory, and a disk used for virtual memory. If a referenced word is in the cache, 20 ns are required to access it. If it is in main memory but not in the cache, 60 ns are needed to load it into the ... 9 and the main memory hit ratio is 0.6.What is the average time in nanoseconds required to access a referenced word on this system?

A computer has a cache, main memory, and a disk used for virtual memory. If a referenced word is in the cache, 20 ns are required to access it. If it is in main memory bu...

dd

412 views

dd asked Dec 18, 2016

5 votes

1 answer

561

Cache memory
Cache memory with a line size of $\large\color{maroon}{\text{32}}$B. In a cache miss situation block of words are loaded from Main memory to cache and then accessed from the cache. $A$ ... should get on average before being replaced such that write back policy becomes more effective than write-through?

Cache memory with a line size of $\large\color{maroon}{\text{32}}$B. In a cache miss situation block of words are loaded from Main memory to cache and then accessed from ...

dd

612 views

dd asked Dec 18, 2016

3 votes

1 answer

562

William Stalling cache memory || 4.21
Consider a $\color{maroon}{\text{single-level cache}}$ with an access time of $2.5$ ns, a line size of $64$ bytes, and a hit ratio of $\large\color{maroon}{\text{H } = 0.95}$. Main memory uses a block transfer capability that has a ... size to $128$ bytes increases the $\large\color{marron}{\text{H}}$ to $0.97$. Does this reduce the average memory access time?

Consider a $\color{maroon}{\text{single-level cache}}$ with an access time of $2.5$ ns, a line size of $64$ bytes, and a hit ratio of $\large\color{maroon}{\text{H } = ...

dd

1.3k views

dd asked Dec 18, 2016

1 votes

1 answer

563

Coa+ Stalls+ Speed up

Rahul Jain25

794 views

Rahul Jain25 asked Dec 11, 2016

1 votes

1 answer

564

MadeEasy Workbook [2017] Q33 - Efficiency of Cache using Write Through Scheme
Data: Hit Ratio for Read Op - 80% Hit Ratio for Write Op - 90% There are 30% updations. Cache Access time: 20ns [CMAT] MM Access Time - 100ns [MMAT] If there is a miss (either for read or write entire 2 block word block ... i.e. 11.9 Million Ops per sec Please tell me if it's right or wrong or how it will be solved.

Data:Hit Ratio for Read Op - 80%Hit Ratio for Write Op - 90%There are 30% updations.Cache Access time: 20ns [CMAT]MM Access Time - 100ns [MMAT]If there is a miss (either ...

Shailendra1993

1.2k views

Shailendra1993 asked Dec 11, 2016

0 votes

0 answers

565

Cache+memory
I am not understanding how options are given because even when one miss will occur entire cache block will be accessed, so 128 B will be accessed.

I am not understanding how options are given because even when one miss will occur entire cache block will be accessed, so 128 B will be accessed.

Rahul Jain25

335 views

Rahul Jain25 asked Dec 9, 2016

21 votes

4 answers

566

MadeEasy Test Series: CO & Architecture - Cache Memory
Suppose that in 250 memory references there are 30 misses in first level cache and 10 misses in second level cache. Assume that miss penalty from L$_2$ cache memory are 50 cycles. The hit time of L$_2$ cache is 10 cycles. The ... with given misses = 1800 stall cycles = 1800-1250 = 550 number of stalls/instruction= 550/200 = 2.75 please verify

Suppose that in 250 memory references there are 30 misses in first level cache and 10 misses in second level cache. Assume that miss penalty from L$_2$ cache memory are 5...

Anusha Motamarri

3.8k views

Anusha Motamarri asked Dec 9, 2016

1 votes

3 answers

567

MadeEasy Test Series: CO & Architecture - Cache Memory
Question :

Question :

dd

1.1k views

dd asked Dec 8, 2016

0 votes

0 answers

568

MadeEasy Test Series: CO & Architecture - Cache Memory
tag bits =4. means 0.5 Bytes size of tag memory = 0.5* number of blocks=0.5* 2^9 Bytes= 0.25 KB ryt?

tag bits =4. means 0.5 Bytessize of tag memory = 0.5* number of blocks=0.5* 2^9 Bytes= 0.25 KB ryt?

Anusha Motamarri

387 views

Anusha Motamarri asked Dec 5, 2016

1 votes

0 answers

569

MadeEasy Test Series: CO & Architecture - Cache Memory
block size = 4B no.of blocks in cache= 4 number of sets =1 which means its fully associative, main memory addresse 100 to 103 reside in block 26 104 to 107- Block 27 108 to 10A -block 28 in main memory converting given addresses to blocks 100 104 ... 27, 28, 27, 26, 28, 26 arent there only 3 misses? i got miss ratio = 3/10 = 0.3 please verify

block size = 4Bno.of blocks in cache= 4number of sets =1 which means its fully associative,main memory addresse 100 to 103 reside in block 26 104 to 107- Block 27108 to 1...

Anusha Motamarri

423 views

Anusha Motamarri asked Dec 5, 2016

2 votes

2 answers

570

Calicut Gate Academy Test Series
Common Data For Questions 1 and Question 2 Direct Mapping cache given below 17-tag | 10-block | 5-word , 2 to 1 MUX / OR has latency of 0.6ns ,k-bit comparator has katency of k/10 ns Question 1 If a two- way set associative cache is constructed ... Number of MUX/OR and Compators Needed in Direct Mapped Cache (#MUX/OR , Comparator) are (1,17) (17,1) (1024,1) None

Common Data For Questions 1 and Question 2 Direct Mapping cache given below 17-tag | 10-block | 5-word , 2 to 1 MUX / OR has latency of 0.6ns ,k-bit comparator has katen...

PEKKA

1.3k views

PEKKA asked Dec 4, 2016

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