Recent questions tagged cache-memory

explain
Consider the given two statements S1 and S2 S1: If compulsory misses are most common then the designers should consider to increase the cache line size to take better advantage of locality. S2: If capacity misses are most common then the designer should increase the cache ... of the following is correct? S1 is true, S2 is false S2 is true, S1 is false Both are false Both are true

4.4k views

Sourabh Kumar asked Jun 27, 2015

3 votes

3 answers

692

Consider the given two statements S1 and S2S1: If compulsory misses are most common then the designers should consider to increase the cache line size to take better adva...

3.3k views

Sourabh Kumar asked Jun 26, 2015

0 votes

0 answers

693

please see it once

if compulsory misses is problem in cache then designer should increase the cache block size to take advantage of better locality

398 views

Sourabh Kumar asked Jun 26, 2015

1 votes

3 answers

694

TRUE OR FALSE

cache memory
A computer system contains a main memory of 32K 16-bit words. It also has a 4Kword cache divided into four-line sets with 64 words per line. Assume that the cache is initially empty. The processor fetches words from locations 0, 1, 2, . . ., ... is 10 times faster than main memory. Estimate the improvement resulting from the use of the cache. Assume an LRU policy for block replacement.

874 views

Sourabh Kumar asked Jun 25, 2015

6 votes

2 answers

695

A computer system contains a main memory of 32K 16-bit words. It also has a 4Kword cache divided into four-line sets with 64 words per line. Assume that the cache is init...

COA
A computer has a cache, main memory, and a disk used for virtual memory. If a referenced word is in the cache, 20 ns are required to access it. If it is in main memory but not in the cache, 60 ns are needed to load it into the cache, and then the ... to access a referenced word on this system ans tavg=Hit_cache*time_cache+(1-Hitcache)(hit_main)[60+20]+(1-hit_cache)(1-hit_mainmmry)[60+12+20]

5.2k views

focus _GATE asked Jun 11, 2015

4 votes

1 answer

696

A computer has a cache, main memory, and a disk used for virtual memory. If a referenced word is in the cache, 20 ns are required to access it. If it is in main memory bu...

consider the following
Consider a single-level cache with an access time of 2.5 ns, a line size of 64 bytes, and a hit ratio of H 0.95. Main memory uses a block transfer capability that has a first word (4 bytes) access time of 50 ns and an access time of 5 ns ... a hit. b. Suppose that increasing the line size to 128 bytes increases the H to 0.97. Does this reduce the average memory access time?

10.0k views

focus _GATE asked Jun 7, 2015

4 votes

1 answer

697

Consider a single-level cache with an access time of 2.5 ns, a line size of 64 bytes, and a hit ratio of H 0.95. Main memory uses a block transfer capability that has a f...

Consider an L1 cache with an access time of 1 ns and a hit ratio of H 0.95.
Consider an L1 cache with an access time of 1 ns and a hit ratio of H 0.95. Suppose that we can change the cache design (size of cache, cache organization) such that we increase H to 0.97, but ... so we have to search throught the cache which wiill increase the cache accees time ..and performance will decreases.....

8.1k views

focus _GATE asked Jun 7, 2015

3 votes

1 answer

698

Consider an L1 cache with an access time of 1 ns and a hit ratio of H 0.95. Suppose that we can change the cache design (size of cache, cache organization) such that we i...

Consider a computer with the following characteristics:
Consider a computer with the following characteristics: total of 1Mbyte of main memory; word size of 1 byte; block size of 16 bytes; and cache size of 64 Kbytes. (a). For the main memory address CABBE, give the corresponding tag and offset values for a fully-associative cache and tag,set and word offset for a two-way set-associative cache.

4.3k views

focus _GATE asked Jun 7, 2015

1 votes

1 answer

699

Consider a computer with the following characteristics: total of 1Mbyte of main memory; word size of 1 byte; block size of 16 bytes; and cache size of 64 Kbytes.(a). For ...

Given the following specifications for an external cache memory
Given the following specifications for an external cache memory: four-way set associative; line size of two 16-bit words; able to accommodate a total of 4K 32-bit words from main memory; used with a 16 ... . Design the cache structure with all pertinent information and show how it interprets the processor’s addresses.

3.8k views

focus _GATE asked Jun 7, 2015

1 votes

1 answer

700

Given the following specifications for an external cache memory: four-way set associative; line size of two 16-bit words; able to accommodate a total of 4K 32-bit words f...

Consider a 32-bit microprocessor that has an on-chip 16-KByte four-way set-associative cache.
Consider a 32-bit microprocessor that has an on-chip 16-KByte four-way set-associative cache. Assume that the cache has a line size of four 32-bit words. Draw a block diagram of this cache showing ... used to determine a cache hit/miss. Where in the cache is the word from memory location ABCDE8F8 mapped?

5.8k views

focus _GATE asked Jun 7, 2015

4 votes

1 answer

701

Consider a 32-bit microprocessor that has an on-chip 16-KByte four-way set-associative cache. Assume that the cache has a line size of four 32-bit words. Draw a block dia...

16 KB, 4-way set-associative cache, 32-bit address, byte addressable memory, 32-byte cache blocks/lines

14.1k views

focus _GATE asked Jun 7, 2015

0 votes

1 answer

702

16 KB, 4-way set-associative cache, 32-bit address, byte addressable memory, 32-byte cache blocks/linesHow many tag bits?Where would you find the word at address 0x200356...

64 word cache and Main memory is divided into 16 words block.
64 word cache and main memory is divided into 16 words block.The access time of cache is 10ns/word and for main memory is 50ns/word. The hit ratio for read operation is .8 and write operation is.9. Whenever there is ... to cache for read and write operation. 40% reference is for write operation. Avg access time if write through is used.

6.5k views

focus _GATE asked Jun 5, 2015

19 votes

2 answers

703

64 word cache and main memory is divided into 16 words block.The access time of cache is 10ns/word and for main memory is 50ns/word. The hit ratio for read operation is ....

Ram Sharma1

6.8k views

Ram Sharma1 asked May 20, 2015

3 votes

1 answer

704

Cache Coherence
Given a virtual memory system with a TLB, a cache, and a page table, assume the following: A TLB hit requires 5ns. A cache hit requires 12ns. A memory reference requires 25ns. A disk reference requires 200ms (this includes updating the page table, ... down the equation to calculate the effective access time. please help and what we do mean by access is not restarted in above .

Given a virtual memory system with a TLB, a cache, and a page table, assume the following: •A TLB hit requires 5ns. •A cache hit requires 12ns. •A memory reference ...

spriti1991

1.5k views

spriti1991 asked Mar 20, 2015

1 votes

1 answer

705

Mapping Strategies
A 2-way set associative cache consists of four sets. Main memory contains 2K blocks of eight words each. a) Show the main memory address format that allows us to map addresses from main memory to cache. Be sure to include the fields as well as their sizes. b) ... . i am sorry to write such a big content . But this question need and to show my way of approaching towards sums :)

A 2-way set associative cache consists of four sets. Main memory contains 2K blocks of eight words each. a) Show the main memory address format that allows us to map addr...

spriti1991

2.0k views

spriti1991 asked Mar 20, 2015

29 votes

4 answers

706

GATE CSE 2015 Set 3 | Question: 14
Consider a machine with a byte addressable main memory of $2^{20}$ bytes, block size of $16$ bytes and a direct mapped cache having $2^{12}$ cache lines. Let the addresses of two consecutive bytes in main memory be $\textsf{(E201F)}_{16}$ ... $\textsf{(E201F)}_{16}$? $\textsf{E, 201}$ $\textsf{F, 201}$ $\textsf{E, E20}$ $\textsf{2, 01F}$

Consider a machine with a byte addressable main memory of $2^{20}$ bytes, block size of $16$ bytes and a direct mapped cache having $2^{12}$ cache lines. Let the addresse...

go_editor

8.6k views

go_editor asked Feb 14, 2015

35 votes

4 answers

707

GATE CSE 2015 Set 2 | Question: 24
Assume that for a certain processor, a read request takes $50\:\text{nanoseconds}$ on a cache miss and $5\:\text{nanoseconds}$ on a cache hit. Suppose while running a program, it was observed that $80\%$ of the processor's read requests result in a cache hit. The average read access time in nanoseconds is ______.

Assume that for a certain processor, a read request takes $50\:\text{nanoseconds}$ on a cache miss and $5\:\text{nanoseconds}$ on a cache hit. Suppose while running a pro...

go_editor

13.9k views

go_editor asked Feb 12, 2015

22 votes

5 answers

708

GATE IT 2005 | Question: 61
Consider a $2$-way set associative cache memory with $4$ sets and total $8$ cache blocks $(0-7)$ and a main memory with $128$ blocks $(0-127)$. What memory blocks will be present in the cache after the following sequence of memory block references if LRU policy is used for cache block replacement. ... $9$ $16$ $55$ $0$ $5$ $7$ $9$ $16$ $55$ $3$ $5$ $7$ $9$ $16$ $55$

Consider a $2$-way set associative cache memory with $4$ sets and total $8$ cache blocks $(0-7)$ and a main memory with $128$ blocks $(0-127)$. What memory blocks will be...

GATE IT 2004 | Question: 48
Consider a fully associative cache with $8$ cache blocks (numbered $0-7$) and the following sequence of memory block requests: $4, 3, 25, 8, 19, 6, 25, 8, 16, 35, 45, 22, 8, 3, 16, 25, 7$ If LRU replacement policy is used, which cache block will have memory block $7$? $4$ $5$ $6$ $7$

9.0k views

Ishrat Jahan asked Nov 3, 2014

34 votes

3 answers

709

Consider a fully associative cache with $8$ cache blocks (numbered $0-7$) and the following sequence of memory block requests:$4, 3, 25, 8, 19, 6, 25, 8, 16, 35, 45, 22, ...

GATE IT 2004 | Question: 12, ISRO2016-77
Consider a system with $2$ level cache. Access times of Level $1$ cache, Level $2$ cache and main memory are $1$ $ns$, $10$ $ns$, and $500$ $ns$ respectively. The hit rates of Level $1$ and Level $2$ caches are $0.8$ and $0.9$, respectively. What is the average access time of the system ignoring the search time within the cache? $13.0$ $12.8$ $12.6$ $12.4$

15.0k views

Ishrat Jahan asked Nov 2, 2014

53 votes

8 answers

710

Consider a system with $2$ level cache. Access times of Level $1$ cache, Level $2$ cache and main memory are $1$ $ns$, $10$ $ns$, and $500$ $ns$ respectively. The hit rat...

GATE IT 2006 | Question: 43
A computer system has a level-$1$ instruction cache ($1$-cache), a level-$1$ data cache ($D$-cache) and a level-$2$ cache ($L2$-cache) with the following specifications: \begin{array}{|l|c|c|c|} \hline \text {} & \textbf{Capacity }& \textbf{Mapping Method} & \textbf{Block ... $18$-bit, $1$ K x $16$-bit $1$ K x $18$-bit, $512$ x $18$-bit, $1$ K x $18$-bit

29.6k views

Ishrat Jahan asked Nov 1, 2014

27 votes

2 answers

711

A computer system has a level-$1$ instruction cache ($1$-cache), a level-$1$ data cache ($D$-cache) and a level-$2$ cache ($L2$-cache) with the following specifications:\...

GATE IT 2006 | Question: 42
A cache line is $64$ bytes. The main memory has latency $32$ $ns$ and bandwidth $1$ $GBytes/s$. The time required to fetch the entire cache line from the main memory is: $32$ $ns$ $64$ $ns$ $96$ $ns$ $128$ $ns$

7.2k views

Ishrat Jahan asked Oct 31, 2014

42 votes

2 answers

712

A cache line is $64$ bytes. The main memory has latency $32$ $ns$ and bandwidth $1$ $GBytes/s$. The time required to fetch the entire cache line from the main memory is:$...

GATE IT 2007 | Question: 37
Consider a Direct Mapped Cache with 8 cache blocks (numbered $0-7$). If the memory block requests are in the following order $3, 5, 2, 8, 0, 63, 9,16, 20, 17, 25, 18, 30, 24, 2, 63, 5, 82,17, 24.$ Which of the following memory blocks will not be in the cache at the end of the sequence ? $3$ $18$ $20$ $30$

11.8k views

Ishrat Jahan asked Oct 31, 2014

16 votes

3 answers

713

Consider a Direct Mapped Cache with 8 cache blocks (numbered $0-7$). If the memory block requests are in the following order$3, 5, 2, 8, 0, 63, 9,16, 20, 17, 25, 18, 30, ...

GATE IT 2008 | Question: 81
Consider a computer with a $4$-ways set-associative mapped cache of the following characteristics: a total of $1\;\text{MB}$ of main memory, a word size of $1\;\text{byte}$, a block size of $128$ ... $000011000$ $110001111$ $00011000$ $110010101$

8.0k views

Ishrat Jahan asked Oct 29, 2014

21 votes

4 answers

714

Consider a computer with a $4$-ways set-associative mapped cache of the following characteristics: a total of $1\;\text{MB}$ of main memory, a word size of $1\;\text{by...

GATE IT 2008 | Question: 80
Consider a computer with a $4$-ways set-associative mapped cache of the following characteristics: a total of $1 \ MB$ of main memory, a word size of $1$ byte, a block size of $128$ words and a cache size of $8 \ KB$. The number of bits in the TAG, SET and WORD fields, respectively are: $7, 6, 7$ $8, 5, 7$ $8, 6, 6$ $9, 4, 7$

5.8k views

Ishrat Jahan asked Oct 29, 2014

16 votes

2 answers

715

Consider a computer with a $4$-ways set-associative mapped cache of the following characteristics: a total of $1 \ MB$ of main memory, a word size of $1$ byte, a block ...

GATE CSE 1996 | Question: 26
A computer system has a three-level memory hierarchy, with access time and hit ratios as shown below: ... of less than $100 nsec$? What is the average access time achieved using the chosen sizes of level $1$ and level $2$ memories?

7.0k views

Ishrat Jahan asked Oct 29, 2014

36 votes

5 answers

716

A computer system has a three-level memory hierarchy, with access time and hit ratios as shown below:$$\overset{ \text {Level $1$ (Cache memory)} \\ \text{Access time = ...

GATE CSE 1995 | Question: 2.25
A computer system has a $4 \ K$ word cache organized in block-set-associative manner with $4$ blocks per set, $64$ words per block. The number of bits in the SET and WORD fields of the main memory address format is: $15, 40$ $6, 4$ $7, 2$ $4, 6$

15.1k views

Kathleen asked Oct 9, 2014

23 votes

2 answers

717

A computer system has a $4 \ K$ word cache organized in block-set-associative manner with $4$ blocks per set, $64$ words per block. The number of bits in the SET and WORD...

GATE CSE 1995 | Question: 1.6
The principle of locality justifies the use of: Interrupts DMA Polling Cache Memory

10.8k views

Kathleen asked Oct 8, 2014

25 votes

3 answers

718

The principle of locality justifies the use of:InterruptsDMAPollingCache Memory

GATE CSE 2010 | Question: 48
A computer system has an $L1$ cache, an $L2$ cache, and a main memory unit connected as shown below. The block size in $L1$ cache is $4$ words. The block size in $L2$ cache is $16$ words. The memory access times are $2$ ... $L1$ cache. What is the time taken for this transfer? $2$ nanoseconds $20$ nanoseconds $22$ nanoseconds $88$ nanoseconds

8.7k views

Kathleen asked Oct 8, 2014

80 votes

8 answers

719

A computer system has an $L1$ cache, an $L2$ cache, and a main memory unit connected as shown below. The block size in $L1$ cache is $4$ words. The block size in $L2$ cac...

go_editor

42.6k views

go_editor asked Sep 30, 2014

49 votes

6 answers

720

GATE CSE 1993 | Question: 11
In the three-level memory hierarchy shown in the following table, $p_i$ denotes the probability that an access request will refer to $M_i$ ... a page swap is $T_i$. Calculate the average time $t_A$ required for a processor to read one word from this memory system.

In the three-level memory hierarchy shown in the following table, $p_i$ denotes the probability that an access request will refer to $M_i$.$$\begin{array}{|c|c|c|c|} \hli...