Login
Register
Dark Mode
Brightness
Profile
Edit Profile
Messages
My favorites
My Updates
Logout
Slides
A Simple Illustration
Cache Memory
Recent questions tagged cache-memory
0
votes
0
answers
91
Best Open Video Playlist for Cache Memory Topic | CO & A
Please list out the best free available video playlist for Cache memory from CO & A as an answer here (only one playlist per answer). We'll then select the best playlist and add to GO classroom video lists. You can add ... ) but standard ones are more likely to be selected as best. For the full list of selected videos please see here
Please list out the best free available video playlist for Cache memory from CO & A as an answer here (only one playlist per answer). We'll then select the best playlist ...
makhdoom ghaya
154
views
makhdoom ghaya
asked
Aug 16, 2022
Study Resources
go-classroom
video-links
missing-videos
free-videos
cache-memory
+
–
0
votes
0
answers
92
cache memory
Consider a cache organization employing a line of 64B and main memory that requires 40ns to transfer a 2B word. What is the minimum average number of times a cache line must be made dirty for write-back policy to be more efficient than write though policy, for any line which is written at-least-once
Consider a cache organization employing a line of 64B and main memory that requires 40ns to transfer a 2B word. What is the minimum average number of times a cache line m...
kathan Mistry
347
views
kathan Mistry
asked
Aug 9, 2022
CO and Architecture
co-and-architecture
cache-memory
numerical-answers
+
–
0
votes
0
answers
93
#conflict misses
Fully associative cache yields no conflict misses?? Or yields very very very very less conflict misses
Fully associative cache yields no conflict misses?? Or yields very very very very less conflict misses
Subbu.
558
views
Subbu.
asked
Jul 24, 2022
CO and Architecture
co-and-architecture
cache-memory
+
–
0
votes
0
answers
94
online lectures
A CPU has a cache of 64 bytes. The main memory has K-banks, each bank can store C-bytes of data. The consecutive C' byte chunks are mapped to consecutive banks with wrap around manner , all K-banks can accessed in parallel. However the two accesses for ... and this takes (k/2)ns. Latency of each addressing bank is 80ns. How much time is required to transfer initial block of cache,
A CPU has a cache of 64 bytes. The main memory has K-banks, each bank can store C-bytes of data. The consecutive ‘C’ byte chunks are mapped to consecutive banks with ...
JAINchiNMay
303
views
JAINchiNMay
asked
Jul 24, 2022
CO and Architecture
memory-interleaving
cache-memory
computer-organisation
+
–
0
votes
0
answers
95
#MemoryAccess
What is the difference between hit time and access time ? What is the difference between access time and transfer time? In avg memory access.. Does access time includes transfer time ,that means access time =memory latency + transfer time??… Note: Transferring about mm to cache .. don't include disk acces and transfer time..
What is the difference between hit time and access time ?What is the difference between access time and transfer time? In avg memory access..Does access time includes tra...
Subbu.
217
views
Subbu.
asked
Jul 23, 2022
CO and Architecture
co-and-architecture
cache-memory
+
–
0
votes
0
answers
96
Quantify the effect on performance that result from the use of a cache in the case of a program that has a total of 500
Quantify the effect on performance that results from the use of a cache in the case of a program that has a total of 500 instructions, including a 100-instruction loop th...
Anshul kumar singh
696
views
Anshul kumar singh
asked
Jul 18, 2022
CO and Architecture
co-and-architecture
carl-hamacher
cache-memory
+
–
21
votes
1
answer
97
GATE CSE 2022 | Question: 14
Let $\text{WB}$ and $\text{WT}$ be two set associative cache organizations that use $\text{LRU}$ algorithm for cache block replacement. $\text{WB}$ is a write back cache and $\text{WT}$ ... cache to main memory. A read miss in $\text{WB}$ will never lead to eviction of a dirty block from $\text{WB}.$
Let $\text{WB}$ and $\text{WT}$ be two set associative cache organizations that use $\text{LRU}$ algorithm for cache block replacement. $\text{WB}$ is a write back cache ...
Arjun
7.8k
views
Arjun
asked
Feb 15, 2022
CO and Architecture
gatecse-2022
co-and-architecture
cache-memory
multiple-selects
1-mark
+
–
13
votes
2
answers
98
GATE CSE 2022 | Question: 23
A cache memory that has a hit rate of $0.8$ has an access latency $10 \; \text{ns}$ and miss penalty $100 \; \text{ns}.$ An optimization is done on the cache to reduce the miss rate. However, the optimization results ... (rounded off to two decimal places) needed after the optimization such that it should not increase the average memory access time is _______________.
A cache memory that has a hit rate of $0.8$ has an access latency $10 \; \text{ns}$ and miss penalty $100 \; \text{ns}.$ An optimization is done on the cache to reduce th...
Arjun
9.1k
views
Arjun
asked
Feb 15, 2022
CO and Architecture
gatecse-2022
numerical-answers
co-and-architecture
cache-memory
1-mark
+
–
2
votes
1
answer
99
GATE Overflow Test Series | Mock GATE | Test 6 | Question: 40
Consider a CPU with an average CPI of $1.6$ ... being $0.1$ (round off to $2$ decimal places). Assume no penalty for instruction fetches working via a separate instruction cache.
Consider a CPU with an average CPI of $1.6$ when all memory accesses hit on the cache.Assume an instruction mix$$\begin{array}{|c | c|}\hline\text{ALU }& 55\%\\\text{LOAD...
Arjun
290
views
Arjun
asked
Jan 30, 2022
CO and Architecture
go2025-mockgate-6
co-and-architecture
cache-memory
numerical-answers
normal
2-marks
+
–
2
votes
1
answer
100
Made Easy Test Series
Consider a fully associative cache with 6 cache blocks (0 to 5) and the following sequence of memory block requests: 5, 4, 29, 18, 21, 7, 25, 18, 16, 35, 45, 22, 7, 19 If LRU replacement policy is used, which cache block is used for memory block 19? Assume initially 6 blocks are placed in a cache according to lexicographic order of cache index.
Consider a fully associative cache with 6 cache blocks (0 to 5) and the following sequence of memory block requests:5, 4, 29, 18, 21, 7, 25, 18, 16, 35, 45, 22, 7, 19If L...
LRU
539
views
LRU
asked
Jan 20, 2022
CO and Architecture
made-easy-test-series
co-and-architecture
cache-memory
+
–
5
votes
3
answers
101
Made Easy Test Series
Consider the following statements: S1 : Direct mapped caches do not need a cache block replacement policy, whereas fully associative cache need. S2 : Direct mapped cache, may produce more misses if programs refers to memory words that occupy a same tag value. Which of the following options is correct?
Consider the following statements:S1 : Direct mapped caches do not need a cache block replacement policy, whereas fully associative cache need. S2 : Direct mapped cache, ...
LRU
782
views
LRU
asked
Jan 20, 2022
CO and Architecture
made-easy-test-series
co-and-architecture
cache-memory
+
–
0
votes
3
answers
102
Appllied Gate Test Series
A hierarchical memory system that uses cache memory has cache access time of 80 nanoseconds, main memory access time of 200 nanoseconds, 85% of memory requests are for read, hit ratio of 0.9 for read access and the write-through scheme is used. What will be the average access time of the system both for read and write requests ?
A hierarchical memory system that uses cache memory has cache access time of 80 nanoseconds, main memory access time of 200 nanoseconds, 85% of memory requests are for re...
Sagar475
1.0k
views
Sagar475
asked
Jan 16, 2022
CO and Architecture
co-and-architecture
cache-memory
write-through
+
–
1
votes
0
answers
103
Applied Test Series
Consider a memory system that uses a 32-bit address to address at the byte level, plus a cache that uses a 64-byte line size. Assume a four-way set-associative cache with a tag field in the address of 9 bits. The total number of cache lines/ blocks in the cache are_____
Consider a memory system that uses a 32-bit address to address at the byte level, plus a cache that uses a 64-byte line size. Assume a four-way set-associative cache with...
LRU
365
views
LRU
asked
Jan 14, 2022
CO and Architecture
test-series
co-and-architecture
cache-memory
+
–
0
votes
1
answer
104
Testbook test series
Can anyone please solve this?
Can anyone please solve this?
Shoto
426
views
Shoto
asked
Jan 14, 2022
CO and Architecture
testbook-test-series
co-and-architecture
cache-memory
+
–
1
votes
1
answer
105
APPLIED ROOTS Multisubject test
Consider a 32-bit microprocessor that has an on-chip 16-KByte four-way set-associative cache. Assume that the cache has a line size of four 32-bit words.Where in the cache (Set number in decimal) is the word from memory location ABCDE888 mapped?
Consider a 32-bit microprocessor that has an on-chip 16-KByte four-way set-associative cache. Assume that the cache has a line size of four 32-bit words.Where in the cach...
samir757
466
views
samir757
asked
Dec 23, 2021
CO and Architecture
co-and-architecture
cache-memory
+
–
0
votes
2
answers
106
Testbook Test Series
In designing a computer’s cache system,
In designing a computer’s cache system,
rsansiya111
394
views
rsansiya111
asked
Dec 23, 2021
CO and Architecture
testbook-test-series
co-and-architecture
cache-memory
+
–
3
votes
1
answer
107
NPTEL Assignment
Consider a direct-mapped cache with 64 blocks and a block size of 16 bytes. Byte address 1200 will map to block number ………… of the cache.
Consider a direct-mapped cache with 64 blocks and a block size of 16 bytes. Byte address 1200 will map to block number ………… of the cache.
LRU
1.2k
views
LRU
asked
Dec 4, 2021
CO and Architecture
nptel-quiz
co-and-architecture
cache-memory
+
–
1
votes
1
answer
108
Applied Test Series
The cache takes 2 cycles to access and has a 5% miss rate, main memory takes 100 cycles to access and has an 8% miss rate, and the disk takes 10,000 cycles to access. The average memory access time for a given system is____ (in cycles)
The cache takes 2 cycles to access and has a 5% miss rate, main memory takes 100 cycles to access and has an 8% miss rate, and the disk takes 10,000 cycles to access. The...
LRU
380
views
LRU
asked
Dec 4, 2021
CO and Architecture
test-series
co-and-architecture
cache-memory
+
–
1
votes
1
answer
109
Applied Test Series
A cache memory system with capacity of N words and block size of B words is to be designed. If it is designed as a direct mapped cache, the length of the TAG field is 14 bits. If it is designed as a 4-way set associative cache, the length of the TAG field will be ………… bits.
A cache memory system with capacity of N words and block size of B words is to be designed. If it is designed as a direct mapped cache, the length of the TAG field is 14 ...
LRU
413
views
LRU
asked
Dec 4, 2021
CO and Architecture
test-series
co-and-architecture
cache-memory
+
–
1
votes
1
answer
110
Applied Test Series
Consider a machine with a byte addressable main memory of 216 bytes and block size of 8 bytes. Assume that a 2-way associative cache consisting of 32 lines is used with this machine. A 16-bit memory address divided into tag, set number, and byte ... sequence of addresses the number of misses are____ 0001 0001 0001 1011 1100 0011 0011 0100 1101 0000 0001 1101 1010 1010 1010 1010
Consider a machine with a byte addressable main memory of 216 bytes and block sizeof 8 bytes. Assume that a 2-way associative cache consisting of 32 lines is used with th...
LRU
718
views
LRU
asked
Dec 4, 2021
CO and Architecture
test-series
co-and-architecture
cache-memory
+
–
0
votes
1
answer
111
testseries
Direct mapped cache, may produce more misses if programs refers to memory words that occupy a same tag value?? is this statement is correct or not??? give a reason??
Direct mapped cache, may produce more misses if programs refers to memory words that occupy a same tag value??is this statement is correct or not??? give a reason??
Abhishek tarpara
206
views
Abhishek tarpara
asked
Dec 1, 2021
CO and Architecture
cache-memory
test-series
co-and-architecture
made-easy-test-series
+
–
0
votes
0
answers
112
Associative Cache Memory
An eight-way set-associative cache is used in a computer in which the real memory size is 232 bytes. The line size is 16 bytes, and there are 210 lines per set. Calculate the cache size and tag length. Source
An eight-way set-associative cache is used in a computer in which the real memory size is 232 bytes. The line size is 16 bytes, and there are 210 lines per set. Calculate...
Jasmeet Kaur
546
views
Jasmeet Kaur
asked
Nov 27, 2021
CO and Architecture
co-and-architecture
cache-memory
+
–
2
votes
2
answers
113
Applied Test Series
Consider the following memories with their miss rates and hit times Then the average memory access time is ______ (in ns)
Consider the following memories with their miss rates and hit times Then the average memory access time is ______ (in ns)
LRU
530
views
LRU
asked
Nov 5, 2021
CO and Architecture
test-series
co-and-architecture
cache-memory
effective-memory-access
+
–
3
votes
1
answer
114
Applied Test Series
Consider a memory system that uses a 32-bit address to address at the byte level, plus a cache that uses a 64-byte line size. Assume a four-way set-associative cache with a tag field in the address of 9 bits. The total number of cache lines/ blocks in the cache are_____
Consider a memory system that uses a 32-bit address to address at the byte level, plus a cache that uses a 64-byte line size. Assume a four-way set-associative cache with...
LRU
951
views
LRU
asked
Oct 8, 2021
CO and Architecture
test-series
co-and-architecture
cache-memory
+
–
18
votes
4
answers
115
GATE CSE 2021 Set 2 | Question: 19
Consider a set-associative cache of size $\text{2KB (1KB} =2^{10}$ bytes$\text{)}$ with cache block size of $64$ bytes. Assume that the cache is byte-addressable and a $32$ -bit address is used for accessing the cache. If the width of the tag field is $22$ bits, the associativity of the cache is _________
Consider a set-associative cache of size $\text{2KB (1KB} =2^{10}$ bytes$\text{)}$ with cache block size of $64$ bytes. Assume that the cache is byte-addressable and a $3...
Arjun
7.2k
views
Arjun
asked
Feb 18, 2021
CO and Architecture
gatecse-2021-set2
numerical-answers
co-and-architecture
cache-memory
1-mark
+
–
18
votes
2
answers
116
GATE CSE 2021 Set 2 | Question: 27
Assume a two-level inclusive cache hierarchy, $L1$ and $L2$, where $L2$ is the larger of the two. Consider the following statements. $S_1$: Read misses in a write through $L1$ cache do not result in writebacks of dirty lines to the $L2$ $S_2$: Write ... false $S_1$ is false and $S_2$ is true $S_1$ is true and $S_2$ is true $S_1$ is false and $S_2$ is false
Assume a two-level inclusive cache hierarchy, $L1$ and $L2$, where $L2$ is the larger of the two. Consider the following statements.$S_1$: Read misses i...
Arjun
8.1k
views
Arjun
asked
Feb 18, 2021
CO and Architecture
gatecse-2021-set2
co-and-architecture
cache-memory
2-marks
+
–
3
votes
4
answers
117
GATE CSE 2021 Set 1 | Question: 22
Consider a computer system with a byte-addressable primary memory of size $2^{32}$ bytes. Assume the computer system has a direct-mapped cache of size $\text{32 KB}$ ($\text{1 KB}$ = $2^{10}$ bytes), and each cache block is of size $64$ bytes. The size of the tag field is __________ bits.
Consider a computer system with a byte-addressable primary memory of size $2^{32}$ bytes. Assume the computer system has a direct-mapped cache of size $\text{32 KB}$ ($\t...
Arjun
5.4k
views
Arjun
asked
Feb 18, 2021
CO and Architecture
gatecse-2021-set1
co-and-architecture
cache-memory
numerical-answers
1-mark
+
–
4
votes
1
answer
118
GATE Overflow Test Series | Mock GATE | Test 5 | Question: 50
Consider the C code fragment given below: #define N 1000 double a[N][N], d=0; .... for (j = 0; j < N; j++) for (i = 0; i < N; i++) d += a[i][j]; The elements of $a$ are $8$ bytes ... a[i][j]; Determine the percentage reduction in cache misses assuming an 8 KB direct-mapped data cache with 64-byte blocks. (Up to one decimal place)
Consider the C code fragment given below:#define N 1000 double a[N][N], d=0; .... for (j = 0; j < N; j++) for (i = 0; i < N; i++) d += a[i][j];The elements of $a$ are $8$...
gatecse
404
views
gatecse
asked
Feb 8, 2021
CO and Architecture
go2025-mockgate-5
numerical-answers
co-and-architecture
cache-memory
2-marks
+
–
4
votes
1
answer
119
GATE Overflow Test Series | Mock GATE | Test 4 | Question: 34
Which one of the following is/are correct? (Mark all the appropriate choices) Compulsory misses can be reduced by increasing the total cache size. Capacity misses can be reduced by increasing the block size. Conflict ... reduced by increasing the value of associativity. Compulsory misses can be reduced by increasing the cache block size.
Which one of the following is/are correct? (Mark all the appropriate choices)Compulsory misses can be reduced by increasing the total cache size.Capacity misses can be re...
gatecse
325
views
gatecse
asked
Feb 1, 2021
CO and Architecture
go2025-mockgate-4
easy
cache-memory
co-and-architecture
multiple-selects
+
–
1
votes
1
answer
120
GATE Overflow Test Series | Mock GATE | Test 4 | Question: 64
Consider a $4$-way set associative cache of size $\text{16 KB}$ and block size $64$ bytes and using $LRU$ ... times. If the number of conflict misses and compulsory misses are $A$ and $B$ respectively, $2A + 3B =$ _______
Consider a $4$-way set associative cache of size $\text{16 KB}$ and block size $64$ bytes and using $LRU$ replacement. Initially the cache is empty. The following sequenc...
gatecse
312
views
gatecse
asked
Feb 1, 2021
CO and Architecture
go2025-mockgate-4
numerical-answers
cache-memory
co-and-architecture
cache-misses
+
–
Page:
« prev
1
2
3
4
5
6
7
8
9
...
25
next »
Email or Username
Show
Hide
Password
I forgot my password
Remember
Log in
Register
