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Recent questions tagged circuitoutput
+1
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2
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1
UGCNETDec2012II1
Consider the circuit shown below. IN a certain steady state, ‘Y’ is at logical ‘l’. What are the possible values of A, B, C? A=0, B=0, C=1 A=0, B=C=1 A=1, B=C=0 A= B=1, C=1
asked
Jul 8, 2016
in
Digital Logic
by
jothee
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105k
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1.7k
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ugcnetdec2012ii
digitallogic
circuitoutput
+6
votes
1
answer
2
ISRO201613
The circuit given in the figure below is An oscillating circuit and its output is square wave The one whose output remains stable in '1' state The one having output remains stable in '0' state has a single pulse of three times propagation delay
asked
Jul 5, 2016
in
Digital Logic
by
jothee
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105k
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2.7k
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isro2016
digitallogic
circuitoutput
+7
votes
2
answers
3
ISRO201610
Consider the following gate network Which one of the following gates is redundant? Gate No. 1 Gate No. 2 Gate No. 3 Gate No. 4
asked
Jul 5, 2016
in
Digital Logic
by
jothee
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105k
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4.2k
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isro2016
digitallogic
circuitoutput
+6
votes
5
answers
4
ISRO201453
Consider the logic circuit given below. The inverter, AND and OR gates have delays of 6, 10 and 11 nanoseconds respectively. Assuming that wire delays are negligible, what is the duration of glitch for Q before it becomes stable? 5 11 16 27
asked
Jul 1, 2016
in
Digital Logic
by
jothee
Veteran
(
105k
points)

3k
views
isro2014
digitallogic
circuitoutput
+3
votes
5
answers
5
ISRO201415
Consider the logic circuit given below: Q=__________? $\bar{A} C + B \bar{C} +CD$ $ABC + \bar{C} D$ $AB + B \bar{C} + B \bar{D}$ $A \bar{B} + A \bar{C} + \bar{C} D$
asked
Jul 1, 2016
in
Digital Logic
by
jothee
Veteran
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105k
points)

2.2k
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isro2014
digitallogic
circuitoutput
+4
votes
1
answer
6
ISRO200827
The output Y of the given circuit 1 0 X X'
asked
Jun 12, 2016
in
Digital Logic
by
jothee
Veteran
(
105k
points)

1.7k
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isro2008
digitallogic
circuitoutput
+5
votes
1
answer
7
ISRO200826
The logic operations of two combinational circuits in FigureI and Figure II are entirely different identical complementary dual
asked
Jun 12, 2016
in
Digital Logic
by
jothee
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(
105k
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1.7k
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isro2008
digitallogic
circuitoutput
+3
votes
2
answers
8
ISRO200812
In the given network of AND and OR gates $f$ can be written as $X_0X_1X_2 \dots X_n + X_1X_2 \dots X_n + X_2X_3 \dots X_n + \dots + X_n$ $X_0X_1 + X_2X_3+ \dots X_{n1}X_n$ $X_0+X_1 + X_2+ \dots +X_n $ $X_0X_1 + X_3 \dots X_{n1}+ X_2X_3 + X_5 \dots X_{n1} + \dots +X_{n2} X_{n1} +X_n$
asked
Jun 11, 2016
in
Digital Logic
by
jothee
Veteran
(
105k
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2k
views
isro2008
digitallogic
circuitoutput
+17
votes
2
answers
9
GATE201151
Consider the following circuit involving three Dtype flipflops used in a certain type of counter configuration. If all the flipflops were reset to $0$ at power on, what is the total number of distinct outputs (states) represented by $PQR$ generated by the counter? $3$ $4$ $5$ $6$
asked
Apr 21, 2016
in
Digital Logic
by
jothee
Veteran
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105k
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2k
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gate2011
digitallogic
circuitoutput
normal
+1
vote
1
answer
10
MadeEasy Test Series: Digital Logic  Circuit Output
Consider the logical circuit shown below: If initially ABC = 000 then after how many clock pulses the circuit will reach its initial stage? a) 5 b) 6 c) 7 d) 8
asked
Jan 10, 2016
in
Digital Logic
by
Sandeep Singh
Loyal
(
7.2k
points)

221
views
digitallogic
circuitoutput
madeeasytestseries
+21
votes
9
answers
11
GATE199363
Multiple choices can be correct. Mark all of them. For the initial state of $000$, the function performed by the arrangement of the $JK$ flipflops in figure is: Shift Register $Mod 3$ Counter $Mod 6$ Counter $Mod 2$ Counter None of the above
asked
Sep 20, 2015
in
Digital Logic
by
jothee
Veteran
(
105k
points)

3.6k
views
gate1993
digitallogic
circuitoutput
normal
+7
votes
2
answers
12
GATE19936.2
If the state machine described in figure should have a stable state, the restriction on the inputs is given by $a.b=1$ $a+b=1$ $\bar{a} + \bar{b} =0$ $\overline{a.b}=1$ $\overline{a+b} =1$
asked
Sep 20, 2015
in
Digital Logic
by
jothee
Veteran
(
105k
points)

1.6k
views
gate1993
digitallogic
normal
circuitoutput
+1
vote
2
answers
13
what is 9 clock cycles what are output at q0 q1 q2?
asked
Sep 4, 2015
in
Digital Logic
by
Ravi Raaja
(
141
points)

387
views
digitallogic
sequential
circuitoutput
+6
votes
2
answers
14
ISRO201421, UGCNETDec2012III23, UGCNETDec2013III22
What are the final values of $Q_1$ and $Q_0$ after 4 clock cycles, if initial values are 00 in the sequential circuit shown below: 11 01 10 00
asked
Jul 17, 2015
in
Digital Logic
by
focus _GATE
Boss
(
20k
points)

4.9k
views
isro2014
digitallogic
circuitoutput
ugcnetdec2012iii
ugcnetdec2013iii
+21
votes
5
answers
15
GATE2005IT43
Which of the following input sequences will always generate a $1$ at the output $z$ ...
asked
Nov 4, 2014
in
Digital Logic
by
Ishrat Jahan
Boss
(
16.3k
points)

5.7k
views
gate2005it
digitallogic
circuitoutput
normal
+16
votes
1
answer
16
GATE2005IT10
A twoway switch has three terminals $a, b$ and $c.$ In ON position (logic value $1$), $a$ is connected to $b,$ and in OFF position, $a$ is connected to $c$. Two of these twoway switches $S1$ and $S2$ are connected to a bulb as shown below. Which of the ... if true, will always result in the lighting of the bulb ? $S1.\overline{S2}$ $S1 + S2$ $\overline {S1\oplus S2}$ $S1 \oplus S2$
asked
Nov 3, 2014
in
Digital Logic
by
Ishrat Jahan
Boss
(
16.3k
points)

1.8k
views
gate2005it
digitallogic
circuitoutput
normal
+22
votes
3
answers
17
GATE2006IT36
The majority function is a Boolean function $f(x, y, z)$ that takes the value 1 whenever a majority of the variables $x,y,z$ are 1. In the circuit diagram for the majority function shown below, the logic gates for the boxes labeled P and Q are, respectively, XOR, AND XOR, XOR OR, OR OR, AND
asked
Oct 31, 2014
in
Digital Logic
by
Ishrat Jahan
Boss
(
16.3k
points)

3k
views
gate2006it
digitallogic
circuitoutput
normal
+23
votes
7
answers
18
GATE2007IT45
The line $T$ in the following figure is permanently connected to the ground. Which of the following inputs $(X_1 X_2 X_3 X_4)$ will detect the fault ? $0000$ $0111$ $1111$ None of these
asked
Oct 30, 2014
in
Digital Logic
by
Ishrat Jahan
Boss
(
16.3k
points)

3.7k
views
gate2007it
digitallogic
circuitoutput
normal
+16
votes
5
answers
19
GATE2007IT40
What is the final value stored in the linear feedback shift register if the input is $101101$? $0110$ $1011$ $1101$ $1111$
asked
Oct 30, 2014
in
Digital Logic
by
Ishrat Jahan
Boss
(
16.3k
points)

1.7k
views
gate2007it
digitallogic
circuitoutput
normal
+18
votes
2
answers
20
GATE2007IT38
The following expression was to be realized using $2$input AND and OR gates. However, during the fabrication all $2$input AND gates were mistakenly substituted by $2$input NAND gates. $(a.b).c + (a'.c).d + (b.c).d + a. d$ What is the function finally realized ? $1$ $a' + b' + c' + d'$ $a' + b + c' + d'$ $a' + b' + c + d'$
asked
Oct 30, 2014
in
Digital Logic
by
Ishrat Jahan
Boss
(
16.3k
points)

1.7k
views
gate2007it
digitallogic
circuitoutput
normal
+14
votes
2
answers
21
GATE2008IT9
What Boolean function does the circuit below realize? $xz + \bar{x}\bar{z}$ $x\bar{z} + \bar{x}{z}$ $\bar{x}\bar{y} + {y}{z}$ $xy + \bar{y}\bar{z}$
asked
Oct 28, 2014
in
Digital Logic
by
Ishrat Jahan
Boss
(
16.3k
points)

2.2k
views
gate2008it
digitallogic
circuitoutput
normal
+10
votes
2
answers
22
GATE199624a
Consider the synchronous sequential circuit in the below figure Draw a state diagram, which is implemented by the circuit. Use the following names for the states corresponding to the values of flipflops as given below. ... $} \\\hline \end{array}$
asked
Oct 10, 2014
in
Digital Logic
by
Kathleen
Veteran
(
52.2k
points)

1.8k
views
gate1996
digitallogic
circuitoutput
normal
+17
votes
2
answers
23
GATE19962.22
Consider the circuit in figure. $f$ implements $\overline{A} \overline{B}C + \overline{A}B \overline{C} + ABC$ $A + B + C$ $A \oplus B \oplus C$ $AB + BC + CA$
asked
Oct 9, 2014
in
Digital Logic
by
Kathleen
Veteran
(
52.2k
points)

2.8k
views
gate1996
digitallogic
circuitoutput
easy
multiplexer
+27
votes
4
answers
24
GATE19962.21
Consider the circuit in below figure which has a four bit binary number $b_3b_2b_1b_0$ as input and a five bit binary number, $d_4d_3d_2d_1d_0$ as output. Binary to Hex conversion Binary to BCD conversion Binary to Gray code conversion Binary to $radix12$ conversion
asked
Oct 9, 2014
in
Digital Logic
by
Kathleen
Veteran
(
52.2k
points)

4.1k
views
gate1996
digitallogic
circuitoutput
normal
+15
votes
2
answers
25
GATE199411
Find the contents of the flipflop $Q_2, Q_1$ and $Q_0$ in the circuit of figure, after giving four clock pulses to the clock terminal. Assume $Q_2Q_1Q_0=000$ initially.
asked
Oct 6, 2014
in
Digital Logic
by
Kathleen
Veteran
(
52.2k
points)

1.2k
views
gate1994
digitallogic
circuitoutput
normal
+14
votes
1
answer
26
GATE19941.8
The logic expression for the output of the circuit shown in figure below is: $\overline{AC} + \overline{BC} +CD$ $\overline{A}C + \overline{B}C + CD$ $ABC +\overline {C}\; \overline{D}$ $\overline{A}\; \overline{B} + \overline{B}\; \overline{C} +CD$
asked
Oct 4, 2014
in
Digital Logic
by
Kathleen
Veteran
(
52.2k
points)

1.8k
views
gate1994
digitallogic
circuitoutput
normal
+11
votes
1
answer
27
GATE199319
A control algorithm is implemented by the NAND – gate circuitry given in figure below, where $A$ and $B$ are state variable implemented by $D$ flipflops, and $P$ is control input. Develop the state transition table for this controller.
asked
Sep 30, 2014
in
Digital Logic
by
Kathleen
Veteran
(
52.2k
points)

1.1k
views
gate1993
digitallogic
circuitoutput
normal
descriptive
+11
votes
2
answers
28
GATE19936.1
Identify the logic function performed by the circuit shown in figure. exclusive OR exclusive NOR NAND NOR None of the above
asked
Sep 30, 2014
in
Digital Logic
by
Kathleen
Veteran
(
52.2k
points)

2.1k
views
gate1993
digitallogic
circuitoutput
normal
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