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Recent questions tagged circuit-output

21 votes
4 answers
91
GATE CSE 2005 | Question: 15
Consider the following circuit. Which one of the following is TRUE? $f$ is independent of $x$ $f$ is independent of $y$ $f$ is independent of $z$ None of $x, y, z$ is redundant
Consider the following circuit. Which one of the following is TRUE?$f$ is independent of $x$$f$ is independent of $y$$f$ is independent of $z$None of $x, y, z$ is red...
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34 votes
2 answers
93
GATE CSE 2006 | Question: 35
Consider the circuit above. Which one of the following options correctly represents $f\left(x,y,z\right)$ $x\bar{z}+xy+\bar{y}z$ $x\bar{z}+xy+\overline{yz}$ $xz+xy+\overline{yz}$ $xz+x\bar{y}+\bar{y}z$
Consider the circuit above. Which one of the following options correctly represents $f\left(x,y,z\right)$$x\bar{z}+xy+\bar{y}z$$x\bar{z}+xy+\overline{yz}$$xz+xy+\overline...
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66 votes
6 answers
94
GATE CSE 2007 | Question: 36
The control signal functions of a $4$-$bit$ binary counter are given below (where $X$ ... through the following sequence: $0, 3, 4$ $0, 3, 4, 5$ $0, 1, 2, 3, 4$ $0, 1, 2, 3, 4, 5$
The control signal functions of a $4$-$bit$ binary counter are given below (where $X$ is “don’t care”):$$\small {\begin{array}{|c|c|c|c|l|}\hline\textbf{Clear}& ...
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44 votes
5 answers
95
GATE CSE 2004 | Question: 61
Consider the partial implementation of a $2-bit$ counter using $T$ flip-flops following the sequence $0-2-3-1-0,$ as shown below. To complete the circuit, the input $X$ should be $Q_2^c$ $Q_2 + Q_1$ $\left(Q_1 + Q_2\right)^c$ $Q_1 \oplus Q_2$
Consider the partial implementation of a $2-bit$ counter using $T$ flip-flops following the sequence $0-2-3-1-0,$ as shown below.To complete the circuit, the input $X$ sh...
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70 votes
5 answers
96
GATE CSE 2006 | Question: 8
You are given a free running clock with a duty cycle of $50\%$ and a digital waveform $f$ which changes only at the negative edge of the clock. Which one of the following circuits (using clocked D flip-flops) will delay the phase of $f$ by $180°$?
You are given a free running clock with a duty cycle of $50\%$ and a digital waveform $f$ which changes only at the negative edge of the clock. Which one of the following...
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37 votes
5 answers
100
GATE CSE 2000 | Question: 2.12
The following arrangement of master-slave flip flops has the initial state of $P, Q$ as $0, 1$ (respectively). After three clock cycles the output state $P, Q$ is (respectively), $1, 0$ $1, 1$ $0, 0$ $0, 1$
The following arrangement of master-slave flip flopshas the initial state of $P, Q$ as $0, 1$ (respectively). After three clock cycles the output state $P, Q$ is (respect...
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27 votes
1 answer
101
GATE CSE 1991 | Question: 5-a
Analyse the circuit in Fig below and complete the following table ${\begin{array}{|c|c|c|}\hline \textbf{a}& \textbf{b}& \bf{ Q_n} \\\hline 0&0\\\ 0&1 \\ 1&0 \\ 1&1 \\ \hline \end{array}}$
Analyse the circuit in Fig below and complete the following table$${\begin{array}{|c|c|c|}\hline\textbf{a}& \textbf{b}& \bf{ Q_n} \\\hline0&0\\\ 0&1 \\ 1&0 \\ 1...
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